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16.2 Power Failure Detection Function
If reset is effected by means of power-on clear, bit 0 (POCM) of the POC status register (POCS) is set to 1. If
reset is effected by the RESET pin or the watchdog timer, however, POCM holds the previous status.
A power failure status can be detected by detecting this POCM after reset by power-on clear has been cleared
(after program execution has been started from address 0000H).
Symbol
7
6
5
POCS
0
0
0
POCM
0
Power-on clear does not occur
Note
1
Reset is effected by power-on clear
Note
The value of this register is set to 03H only when reset is effected through power-on clearing. It is
not reset by the RESET pin or watchdog timer.
Remark The values of the special function registers, other than POCS and PLLUL, at power-on clear are
the same as the values following a reset by the RESET pin or watchdog timer (see Table 16-1).
218
CHAPTER 16 RESET FUNCTION
Figure 16-5. Format of POC Status Register (POCS)
4
3
2
1
0
0
0
0
VM45 POCM
Detection of power-on clear occurrence status
User's Manual U15104EJ2V0UD
Address
After reset
R/W
Note
FF1BH
Retained
R&Reset
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