Interrupt Request Register 1 (Irr1) - Hitachi SH7709S Hardware Manual

6.3.7

Interrupt Request Register 1 (IRR1)

IRR1 is an 8-bit read-only register that indicates whether DMAC or IrDA interrupt requests have
been generated. This register is initialized to H'00 by a power-on reset or manual reset, but is not
initialized in standby mode.
Bit:
TXI1R
Initial value:
R/W:
Bit 7—TXI1 Interrupt Request (TXI1R): Indicates whether a TXI1 (IrDA) interrupt request has
been generated.
Bit 7: TXI1 Description
0 TXI1 interrupt request not generated
1 TXI1 interrupt request generated
Bit 6—BRI1 Interrupt Request (BRI1R): Indicates whether a BRI1 (IrDA) interrupt request has
been generated.
Bit 6: BRI1R Description
0 BRI1 interrupt request not generated
1 BRI1 interrupt request generated
Bit 5—RXI1 Interrupt Request (RXI1R): Indicates whether an RXI1 (IrDA) interrupt request
has been generated.
Bit 5: RXI1R Description
0 RXI1 interrupt request not generated
1 RXI1 interrupt request generated
Bit 4—ERI1 Interrupt Request (ERI1R): Indicates whether an ERI1 (IrDA) interrupt request
has been generated.
Bit 4: ERI1R Description
0 ERI1 interrupt request not generated
1 ERI1 interrupt request generated
144
7 6 5
BRI1R RXI1R
0 0 0
R R R
4 3 2
ERI1R DEI3R DEI2R
0 0 0
R R R
1 0
DEI1R DEI0R
0 0
R R
(Initial value)
(Initial value)
(Initial value)
(Initial value)