0X5306: Pwm Timer Control Register (T16E_Ctl) - Epson S1C17704 Technical Manual

0x5306: PWM Timer Control Register (T16E_CTL)

Register name Address Bit
PWM Timer 0x5306 D15–9 –
Control Register (16 bits)
D8
(T16E_CTL)
D7
D6
D5
D4
D3
D2
D1
D0
D[15:9] Reserved
D8 INITOL: Initial Output Level Bit
Selects an initial output level for timer output.
1 (R/W): High
0 (R/W): Low (default)
The timer output pin goes to the initial output level set using this bit when the timer output is turned off
by writing 0 to OUTEN (D2) or when the timer is reset by writing 1 to T16ERST (D1). However, this
level is inverted if INVOUT (D4) is set to 1.
D7 Reserved
D6 SELFM: Fine Mode Select Bit
Sets fine mode for clock output.
1 (R/W): Fine mode
0 (R/W): Normal output (default)
When SELFM is set to 1, clock output is set in fine mode which allows adjustment of the output signal
duty ratio in units of a half cycle for the input clock.
When SELFM is set to 0, normal clock output will be performed.
D5 CBUFEN: Comparison Buffer Enable Bit
Enables or disables writing to the compare data buffer.
1 (R/W): Enabled
0 (R/W): Disabled (default)
When CBUFEN is set to 1, compare data is read and written from/to the compare data buffer. The con-
tent of the buffer is loaded to the compare data register when the counter is reset by the software or the
compare B signal.
When CBUFEN is set to 0, compare data is read and written from/to the compare data register.
D4 INVOUT: Inverse Output Control Bit
Selects a logic of the output signal.
1 (R/W): Inverted (active low)
0 (R/W): Normal (active high) (default)
By writing 1 to INVOUT, an active-low signal (off level = high) is generated for the TOUT output.
When INVOUT is set to 0, an active-high signal (off level = low) is generated.
Writing 1 to this bit inverts the initial output level set using INITOL (D8) as well.
S1C17704 TECHNICAL MANUAL
Name Function
reserved
INITOL Initial output level
– reserved
SELFM Fine mode select
CBUFEN Comparison buffer enable
INVOUT
Inverse output
CLKSEL Input clock select
OUTEN
Clock output enable
T16ERST Timer reset
T16ERUN
Timer run/stop control
EPSON
13 PWM & CAPTURE TIMER (T16E)
Setting Init. R/W
–
1 High 0 Low
–
1 Fine mode 0 Normal mode
1 Enable 0 Disable
1 Invert 0 Normal
1 External 0 Internal
1 Enable 0 Disable
1 Reset 0 Ignored
1 Run 0 Stop
Remarks
– – 0 when being read.
0 R/W
– – 0 when being read.
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 W 0 when being read.
0 R/W
13-15