Epson S1C17704 Technical Manual page 200

14 8-BIT OSC1 TIMER (T8OSC1)
An interrupt request to the S1C17 Core is accepted only when all the conditions described below are met.
• The interrupt enable bit is set to 1.
• The IE (Interrupt Enable) bit of the PSR (Processor Status Register) in the S1C17 Core is set to 1.
• The 8-bit OSC1 timer interrupt has a higher interrupt level than the value that is set in the IL field of the PSR.
• No other cause of interrupt having higher priority, such as NMI, has occurred.
For details on these interrupt control registers, as well as the device operation when an interrupt has occurred,
see Chapter 6, "Interrupt Controller (ITC)."
Note: The settings shown below are required to manage the cause-of-interrupt occurrence status using
the interrupt flag in the T8OSC1 module.
1. Set the 8-bit OSC1 timer interrupt trigger mode in the ITC to level trigger.
2. After an interrupt occurs, reset the T8OIF interrupt flag of the T8OSC1 module in the interrupt
handler routine (this also resets the interrupt flag in the ITC).
Interrupt vector
The following shows the vector number and vector address for the 8-bit OSC1 timer interrupt:
Vector number: 8 (0x08)
Vector address: 0x8020
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S1C17704 TECHNICAL MANUAL