Epson S1C17704 Technical Manual page 271

PCLK
SPEN
SPI clock (master mode)
SPI_TXD register
SPICLK pin
(CPOL = 0, CPHA = 1)
SPICLK pin
(CPOL = 0, CPHA = 0)
SDI pin
Shift register
SPI_RXD register
SPBSY
SPRBF
Interrupt
Disabling data transmission/reception
After data transfer (both transmission and reception) has finished, write 0 to the SPEN bit to disable data
transmission/reception.
Always make sure that the SPTBE flag is 1 and SPRBF flag is 0 before data transmission/reception is disabled.
When the SPEN bit is set to 0, the transmit and receive data buffers are placed in empty status (data is cleared
if any remains). Furthermore, the data being transferred cannot be guaranteed if SPEN is set to 0 during
transmitting/receiving.
S1C17704 TECHNICAL MANUAL
Write
dummy
A A
D7 D6
Figure 19.5.2 Data Receive Timing Chart
EPSON
Write
dummy
A B B
D0 D7 D6
Data A
Read
19 SPI
B
D0
Data B
19-7