Table of Contents
Advertisement
0x5003: Clock Timer Interrupt Flag Register (CT_IFLG)
Register name Address
Bit
Clock Timer
0x5003
D7–4 –
Interrupt Flag
(8 bits)
D3
Register
D2
(CT_IFLG)
D1
D0
This register indicates the interrupt cause occurrence status by the clock timer 32Hz, 8 Hz, 2 Hz, and 1 Hz signals.
When a clock timer interrupt occurs, read the interrupt flag in this register to determine the cause of interrupt that
has occurred (or frequency). The CTIF∗ bits are the interrupt flags that correspond to 32 Hz, 8 Hz, 2 Hz, and 1 Hz
interrupts respectively. The CTIF∗ bit is set to 1 at the falling edge of the signal if the corresponding CTIE∗ bit
(CT_IMSK register) has been set to 1. At the same time, the clock timer interrupt request signal is output to the
ITC. The interrupt request signal sets the clock timer interrupt flag in the ITC to 1 and an interrupt occurs if other
interrupt conditions meet the ITC and S1C17 Core settings.
The settings shown below are required to manage the cause-of-interrupt occurrence status using this register.
1. Set the clock timer interrupt trigger mode in the ITC to level trigger.
2. After an interrupt occurs, reset the interrupt flag of the CT module in the interrupt handler routine (this also
resets the interrupt flag in the ITC).
The CTIF∗ flags are reset by writing 1.
Note: To avoid occurrence of unnecessary interrupts, be sure to reset the CTIF∗ flags before the clock
timer interrupt is enabled using CTIE∗.
D[7:4]
Reserved
D3
CTIF32: 32 Hz Interrupt Flag
This is the interrupt flag to indicate the 32 Hz interrupt cause occurrence status.
1 (R):
Cause of interrupt has occurred
0 (R):
No cause of interrupt has occurred (default)
1 (W):
Flag is reset
0 (W):
Has no effect
CTIF32 is set to 1 at the falling edge of the 32 Hz signal only when CTIE32 (D3/CT_IMSK register)
has been set to 1.
D2
CTIF8: 8 Hz Interrupt Flag
This is the interrupt flag to indicate the 8 Hz interrupt cause occurrence status.
1 (R):
Cause of interrupt has occurred
0 (R):
No cause of interrupt has occurred (default)
1 (W):
Flag is reset
0 (W):
Has no effect
CTIF8 is set to 1 at the falling edge of the 8 Hz signal only when CTIE8 (D2/CT_IMSK register) has
been set to 1.
D1
CTIF2: 2 Hz Interrupt Flag
This is the interrupt flag to indicate the 2 Hz interrupt cause occurrence status.
1 (R):
Cause of interrupt has occurred
0 (R):
No cause of interrupt has occurred (default)
1 (W):
Flag is reset
0 (W):
Has no effect
CTIF2 is set to 1 at the falling edge of the 2 Hz signal only when CTIE2 (D1/CT_IMSK register) has
been set to 1.
D0
CTIF1: 1 Hz Interrupt Flag
This is the interrupt flag to indicate the 1 Hz interrupt cause occurrence status.
1 (R):
Cause of interrupt has occurred
0 (R):
No cause of interrupt has occurred (default)
1 (W):
Flag is reset
0 (W):
Has no effect
CTIF1 is set to 1 at the falling edge of the 1 Hz signal only when CTIE1 (D0/CT_IMSK register) has
been set to 1.
S1C17704 TECHNICAL MANUAL
Name
Function
reserved
CTIF32
32 Hz interrupt flag
CTIF8
8 Hz interrupt flag
CTIF2
2 Hz interrupt flag
CTIF1
1 Hz interrupt flag
EPSON
Setting
Init. R/W
–
1 Cause of
0 Cause of
interrupt
interrupt not
occurred
occurred
15 CLOCK TIMER (CT)
Remarks
–
–
0 when being read.
0
R/W Reset by writing 1.
0
R/W
0
R/W
0
R/W
15-11
Advertisement
Table of Contents
