0X5060-0X5065; Oscillator - Epson S1C17704 Technical Manual

APPENDIX A LIST OF I/O REGISTERS
0x5060–0x5065
Register name Address Bit
Clock Source 0x5060 D7–1 –
Select Register
(8 bits)
(OSC_SRC) D0
Oscillation 0x5061 D7–6 –
Control Register (8 bits)
D5–4 OSC3WT[1:0] OSC3 wait cycle select
(OSC_CTL)
D3–2 –
D1
D0
Noise Filter 0x5062 D7–2 –
Enable Register (8 bits)
D1
(OSC_NFEN)
D0
LCD Clock 0x5063 D7–5 –
Setup Register (8 bits)
D4–2 LCKDV[2:0] LCD clock division ratio select
(OSC_LCLK)
D1
D0
FOUT Control 0x5064 D7–4 –
Register
(8 bits) D3–2 FOUT3D[1:0] FOUT3 clock division ratio select
(OSC_FOUT)
D1
D0
T8OSC1 Clock 0x5065 D7–4 –
Control Register (8 bits)
D3–1 T8O1CK[2:0] T8OSC1 clock division ratio select T8O1CK[2:0]
(OSC_T8OSC1)
D0
AP-16
Name Function
reserved
CLKSRC System clock source select
reserved
reserved
OSC1EN
OSC1 enable
OSC3EN OSC3 enable
reserved
RSTFE Reset noise filter enable
NMIFE NMI noise filter enable
reserved
LCKSRC LCD clock source select
LCKEN LCD clock enable
reserved
FOUT3E
FOUT3 output enable
FOUT1E FOUT1 output enable
reserved
T8O1CE T8OSC1 clock output enable
Setting
–
1 OSC1 0 OSC3
–
OSC3WT[1:0]
0x3
0x2
0x1
0x0 1024 cycles
–
1 Enable 0 Disable
1 Enable 0 Disable
–
1 Enable 0 Disable
1 Enable 0 Disable
–
LCKDV[2:0] Division ratio
0x7–0x5
0x4 OSC3•1/512
0x3 OSC3•1/256
0x2 OSC3•1/128
0x1 OSC3•1/64
0x0 OSC3•1/32
1 OSC1 0 OSC3
1 Enable 0 Disable
–
FOUT3D[1:0] Division ratio
0x3
0x2
0x1
0x0
1 Enable 0 Disable
1 Enable 0 Disable
–
Division ratio
0x7–0x6
0x5 OSC1•1/32
0x4 OSC1•1/16
0x3
0x2
0x1
0x0
1 Enable 0 Disable
EPSON

Oscillator

Init. R/W Remarks
– – 0 when being read.
0 R/W
– – 0 when being read.
Wait cycle 0x0 R/W
128 cycles
256 cycles
512 cycles
– – 0 when being read.
1 R/W
1 R/W
– – 0 when being read.
1 R/W
0 R/W
– – 0 when being read.
0x0 R/W
reserved
1 R/W
0 R/W
– – 0 when being read.
0x0 R/W
reserved
OSC3•1/4
OSC3•1/2
OSC3•1/1
0 R/W
0 R/W
– – 0 when being read.
0x0 R/W
reserved
OSC1•1/8
OSC1•1/4
OSC1•1/2
OSC1•1/1
0 R/W
S1C17704 TECHNICAL MANUAL