Epson S1C17704 Technical Manual page 214

15 CLOCK TIMER (CT)
EIFT3 is set to 1 at the falling edge of the 32/8/2/1 Hz signal whose interrupt is enabled. If EIEN3 has been set
to 1, the ITC sends an interrupt request to the S1C17 Core. To disable the clock timer interrupt, set EIEN3 to 0.
EIFT3 is always set to 1 by the interrupt signal sent from the CT module, regardless of how EIEN3 is set (even
when set to 0).
EILV3[2:0] sets the interrupt level (0 to 7) of the clock timer interrupt.
An interrupt request to the S1C17 Core is accepted only when all the conditions described below are met.
• The interrupt enable bit is set to 1.
• The IE (Interrupt Enable) bit of the PSR (Processor Status Register) in the S1C17 Core is set to 1.
• The clock timer interrupt has a higher interrupt level than the value that is set in the IL field of the PSR.
• No other cause of interrupt having higher priority, such as NMI, has occurred.
For details on these interrupt control registers, as well as the device operation when an interrupt has occurred,
see Chapter 6, "Interrupt Controller (ITC)."
Note: The settings shown below are required to manage the cause-of-interrupt occurrence status using
the interrupt flags in the CT module.
1. Set the clock timer interrupt trigger mode in the ITC to level trigger.
2. After an interrupt occurs, reset the CTIF∗ interrupt flag of the CT module in the interrupt
handler routine (this also resets the interrupt flag in the ITC).
Interrupt vector
The following shows the vector number and vector address for the clock timer interrupt:
Vector number: 7 (0x07)
Vector address: 0x801c
15-6
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S1C17704 TECHNICAL MANUAL