Details Of Control Registers - Epson S1C17704 Technical Manual

8 CLOCK GENERATOR (CLG)

8.4 Details of Control Registers

Address
0x5080 CLG_PCLK PCLK Control Register
0x5081 CLG_CCLK CCLK Control Register
The following describes each CLG module control register. These are all 8-bit registers.
Note: When setting the registers, be sure to write a 0, and not a 1, for all "reserved bits."
8-4
Table 8.4.1 List of CLG Registers
Register name
Controls the PCLK output.
Configures the CCLK division ratio.
EPSON
Function
S1C17704 TECHNICAL MANUAL