Fine Mode - Epson S1C17704 Technical Manual

12 8-BIT TIMER (T8F)

12.8 Fine Mode

The fine mode provides a function to minimize transfer rate error.
The 8-bit timer can output a programmable clock used as the serial transfer clock for the UART. By selecting
an appropriate prescaler output clock and reload data, the timer output clock can be configured with the desired
frequency. However, an error may be introduced depending on the transfer rate. In fine mode, the counter delays
outputting the underflow pulse to prolong the output clock period. The amount of delay can be specified using the
TFMD[3:0] bits (D[11:8]/T8F_CTL register).
∗ TFMD[3:0]: Fine Mode Setup Bits in the 8-bit Timer Control (T8F_CTL) Register (D[11:8]/0x4206)
The TFMD[3:0] bits specify a pattern of delays to be inserted in a 16-underflow period. The output clock period
will be prolonged for one count clock period per one delay inserted. Also this setting will delay interrupt timings.
TFMD[3:0]
1 2
0x0 – –
0x1 – –
0x2 – –
0x3 – –
0x4 – –
0x5 – –
0x6 – –
0x7 – –
0x8 – D
0x9 – D
0xa – D
0xb – D
0xc – D
0xd – D
0xe – D
0xf – D
Underflow signal (not corrected)
Underflow signal (corrected)
Output clock (not corrected)
Output clock (corrected)
At initial reset, TFMD[3:0] is set to 0x0. No delay will be inserted in this setting.
12-8
Table 12.8.1 Delay Patterns Specified with TFMD[3:0]
3 4 5 6
– – – –
– – – –
– – – –
– – – –
– D – –
– D – –
– D – D
– D – D
– D – D
– D – D
– D – D D
– D – D D
D D – D D
D D – D D
D D D D D
D D D D D
Count clock
15
15
Figure 12.8.1 Delay Cycle Insertion in Fine Mode
EPSON
Underflow number
7 8 9 10 11
– – – – –
– – – – –
– D – – –
– D – – –
– D – – –
– D – – –
– D – – –
– D – D –
– D – D –
– D – D –
D – D –
D – D D
D – D D
D – D D
D – D D
D D D D
D: Indicates that a delay is inserted.
16
16
Delayed
12 13 14 15 16
– – – –
– – – –
– – – –
D – – –
D – – –
D – D –
D – D –
D – D –
D – D –
D – D D
D – D D
D – D D
D – D D
D D D D
D D D D
D D D D
1
1
S1C17704 TECHNICAL MANUAL
–
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D