Epson S1C17704 Technical Manual page 179

Starting clock output
To output the TOUT clock, write 1 to OUTEN (D2/T16E_CTL register). Clock output is stopped by writing 0
to OUTEN and goes to the initial output level according to the set values of INITOL and INVOUT.
∗ OUTEN: Clock Output Enable Bit in the PWM Timer Control (T16E_CTL) Register (D2/0x5306)
Figure 13.6.2 shows the waveform of the output signal.
Compare A signal
Compare B signal
TOUT output (INITOL = 0, INVOUT = 0)
TOUT output (INITOL = 0, INVOUT = 1)
TOUT output (INITOL = 1, INVOUT = 0)
TOUT output (INITOL = 1, INVOUT = 1)
When INVOUT = 0 (active high)
The timer outputs a low level (initial output level when output is started) until the counter becomes equal
to the compare data A set in the T16E_CA register (0x5300). When the counter is incremented to the next
value from the compare data A, the output pin goes high and a cause of compare A interrupt occurs. When
the counter becomes equal to the compare data B set in the T16E_CB register (0x5302), the counter is reset
and the output pin goes low. At the same time a cause of compare B interrupt occurs.
When INVOUT = 1 (active low)
The timer outputs a high level (inverted initial output level when output is started) until the counter becomes
equal to the compare data A set in the T16E_CA register (0x5300). When the counter is incremented to the
next value from the compare data A, the output pin goes low and a cause of compare A interrupt occurs.
When the counter becomes equal to the compare data B set in the T16E_CB register (0x5302), the counter
is reset and the output pin goes high. At the same time a cause of compare B interrupt occurs.
S1C17704 TECHNICAL MANUAL
Input clock
T16ERST
OUTEN
T16ERUN
Counter value 0
Figure 13.6.2 Waveform of PWM & Capture Timer Output
EPSON
13 PWM & CAPTURE TIMER (T16E)
1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1
(When T16E_CA = 3, T16E_CB = 5)
13-7