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Epson S1C63616 Technical Manual

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S1C63616
Technical Manual
Rev.1.0

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  • Page 1 S1C63616 Technical Manual Rev.1.0...
  • Page 2 No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does...
  • Page 3 Configuration of product number Devices 17xxx 00E1 Packing specifications 00 : Besides tape & reel 0A : TCP BL 2 directions 0B : Tape & reel BACK 0C : TCP BR 2 directions 0D : TCP BT 2 directions 0E : TCP BD 2 directions 0F : Tape &...

  • Page 4: Table Of Contents

    SIC63616-(Rev. 1.0) NO. 4 ontents ___________________________________________________ 1 Chapter utline 1.1 Features ......................1 1.2 Block Diagram ....................2 1.3 Pin Layout Diagram ..................3 1.4 Pin Description ....................5 1.5 Mask Option ....................6 _______________________________ 9 Chapter ower upply and nitial eset 2.1 Power Supply ....................
  • Page 5 SIC63616-(Rev. 1.0) NO. 5 (P00-P03, P10-P13, P20-P23 and P40-P43) 4.5 I/O Ports ....44 4.5.1 Configuration of I/O ports ................44 4.5.2 Mask option ....................45 4.5.3 I/O control registers and input/output mode ..........46 4.5.4 Input interface level ..................46 4.5.5 Pull-down during input mode ..............
  • Page 6 SIC63616-(Rev. 1.0) NO. 6 4.10.9 Programming notes ................. 134 4.11 Sound Generator..................135 4.11.1 Configuration of sound generator ............135 4.11.2 Controlling clock manager ..............135 4.11.3 Control of buzzer output ................135 4.11.4 Setting of buzzer frequency and sound level ..........136 4.11.5 Digital envelope ..................
  • Page 7 SIC63616-(Rev. 1.0) NO. 7 7.7 Timing Chart ....................189 7.8 Characteristics Curves (reference value) ..........190 ________________________________________________ 201 Chapter aCkage 8.1 Plastic Package ..................201 8.2 Ceramic Package for Test Samples ............202 ______________________________________________ 203 Chapter ayout 9.1 Diagram of Pad Layout ................203 9.2 Pad Coordinates ..................

  • Page 8: Features

    The S1C63616 is a microcomputer which has a 4-bit CPU S1C63000 as the core CPU, ROM (16,384 words × 13 bits), RAM (2,048 words × 4 bits), multiply-divide circuit, serial interface, watchdog timer, programmable timer, time base counters (2 systems), a dot matrix LCD driver that can drive a maximum 1,280 dots of LCD panel, and an R/f converter that can measure temperature and humidity using sensors such as a thermistor.

  • Page 9: Block Diagram

    SIC63616-(Rev. 1.0) NO. P2 1.2 Block Diagram Code ROM System Reset RESET 16,384 words × 13 bits Control Core CPU S1C63000 Data ROM Interrupt 2,048 words × 4 bits Generator Watchdog 2,048 words × 4 bits Timer OSC1 Clock OSC2 Timer OSC3 OSC4...

  • Page 10: Pin Layout Diagram

    SIC63616-(Rev. 1.0) NO. P3 1.3 Pin Layout Diagram TQFP15-128pin (Plastic Package) OSC2 COM1 COM2 OSC1 COM3 COM4 OSC4 COM5 OSC3 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 COM16/SEG55 SEG6 COM17/SEG54 SEG7 COM18/SEG53 SEG8 COM19/SEG52...

  • Page 11: Sic63616-(Rev. 1.0) No

    SIC63616-(Rev. 1.0) NO. P4 QFP17-144pin (Ceramic Package for Test Samples) N.C. OSC2 N.C. OSC1 N.C. COM0 OSC4 COM1 OSC3 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 SEG0 SEG1 COM16/SEG55 SEG2 COM17/SEG54 SEG3 COM18/SEG53 SEG4 COM19/SEG52 SEG5...

  • Page 12: Pin Description

    SIC63616-(Rev. 1.0) NO. P5 1.4 Pin Description Table 1.4.1 Pin description Pin No. Pin name Function TQFP15-128 QFP17-144 53, 76 59, 85 67, 96 – Power (+) supply pins 39, 56, 80 45, 62, 89 53, 70, 100 – Power (–) supply pins –...

  • Page 13: Chapter 1 O Utline

    The function option generator winfog, that has been prepared as the development software tool of S1C63616, is used for this selection. Mask pattern of the IC is finally generated based on the data created by the winfog. Refer to the "S5U1C63000A Manual"...

  • Page 14: Sic63616-(Rev. 1.0) No

    SIC63616-(Rev. 1.0) NO. P7 <Option List> The following is the option list for the S1C63616. Multiple selections are available in each option item as indicated in the option list. Select the specifications that meet the target system and check the appropriate box. Be sure to record the specifications for unused functions too, according to the instructions provided.
  • Page 15 SIC63616-(Rev. 1.0) NO. P8 6. MULTIPLE KEY ENTRY RESET COMBINATION 1. Not Use 2. Use <P10, P11> 3. Use <P10, P11, P12> 4. Use <P10, P11, P12, P13> 7. MULTIPLE KEY ENTRY RESET TIME AUTHORIZE 1. Not Use 2. Use 8.

  • Page 16: Power Supply

    The S1C63616 operating power voltage is as follows: 1.6 V to 5.5 V 2.1.2 Internal power supply circuit The S1C63616 incorporates the power supply circuit shown in Figure 2.1.2.1. When voltage within the range described above is supplied to V (+) and V (GND), all the voltages needed for the internal circuits are generated internally in the IC.
  • Page 17 . See Chapter 7, "Electri- cal Characteristics" for the voltage values. In the S1C63616, the LCD drive voltage is supplied to the built-in LCD driver which drives the LCD panel connected to the SEG and COM terminals. Notes: • Be sure not to use the V...

  • Page 18: Initial Reset

    SIC63616-(Rev. 1.0) NO. P11 2.2 Initial Reset The S1C63616 should be reset to initialize the internal circuits. There are two ways of doing this. External initial reset by the RESET terminal External initial reset by simultaneous high input to P10–P13 ports (mask option) The circuits are initialized by either (1) or (2).

  • Page 19: Simultaneous High Input To P1X Ports (P10-P13)

    SIC63616-(Rev. 1.0) NO. P12 2.2.2 Simultaneous high input to P1x ports (P10-P13) Another way of executing initial reset externally is to input high level signals simultaneously to the P1x ports (P10–P13) selected by a mask option. Since this initial reset passes through the noise reject circuit, maintain the specified input port terminals at high level for at least 1.5 msec (when the oscillation frequency f is 32.768 kHz) during normal OSC1...

  • Page 20: Terminal Settings At Initial Resetting

    SIC63616-(Rev. 1.0) NO. P13 2.2.4 Terminal settings at initial resetting The I/O port (P) terminals are shared with special output terminals and input/output terminals of the serial interface, R/f converter, stopwatch timer and programmable timer (event counter). These functions are selected by the software. At initial reset, these terminals are configured to the general purpose I/O port terminals.

  • Page 21: Chapter 3 Cpu, Rom, Ram

    The core CPU can linearly access the program space up to step FFFFH from step 0000H, however, the program area of the S1C63616 is step 0000H to step 3FFFH. The program start address after initial reset is assigned to step 0110H. The non-maskable interrupt (NMI) vector and hardware interrupt vectors are al- located to step 0100H and steps 0101H–010FH, respectively.

  • Page 22: Data Rom

    SIC63616-(Rev. 1.0) NO. P15 (3) Subroutine calls use 4 words (for PC evacuation) in the stack area for 16-bit data (SP1). Interrupts use 4 words (for PC evacuation) in the stack area for 16-bit data (SP1) and 1 word (for F register evacuation) in the stack area for 4-bit data.

  • Page 23: Memory Map

    The peripheral circuits of S1C63616 (timer, I/O, etc.) are interfaced with the CPU in the memory mapped I/ O method. Thus, all the peripheral circuits can be controlled by accessing the I/O memory on the memory map using the memory operation instructions. The following sections explain the detailed operation of each peripheral circuit.
  • Page 24 SIC63616-(Rev. 1.0) NO. P17 Table 4.1.1 (a) I/O memory map (FF00H-FF16H) Register Address Comment ∗1 Name Init CLKCHG OSC3 OSC1 CPU clock switch CLKCHG OSCC OSCC OSC3 oscillation On/Off FF00H ∗3 ∗2 – Unused ∗3 ∗2 – Unused ∗3 ∗2 –...
  • Page 25 SIC63616-(Rev. 1.0) NO. P18 Table 4.1.1 (b) I/O memory map (FF18H-FF20H) Register Address Comment ∗1 Name Init PTPS03 Programmable timer 0 count clock frequency selection [PTPS03–00] PTPS03 PTPS02 PTPS01 PTPS00 PTPS02 Frequency /256 OSC1 OSC1 OSC1 OSC1 OSC1 FF18H [PTPS03–00] PTPS01 Frequency /256...
  • Page 26 SIC63616-(Rev. 1.0) NO. P19 Table 4.1.1 (c) I/O memory map (FF21H-FF28H) Register Address Comment ∗1 Name Init IOC03 Output Input P03 I/O control register functions as a general-purpose register when R/f or BZ is used IOC03 IOC02 IOC01 IOC00 IOC02 Output Input P02 I/O control register...
  • Page 27 SIC63616-(Rev. 1.0) NO. P20 Table 4.1.1 (d) I/O memory map (FF29H-FF2BH) Register Address Comment ∗1 Name Init IOC23 Output Input P23 I/O control register functions as a general-purpose register when SIF or FOUT is used IOC23 IOC22 IOC21 IOC20 IOC22 Output Input P22 I/O control register...
  • Page 28 SIC63616-(Rev. 1.0) NO. P21 Table 4.1.1 (e) I/O memory map (FF30H-FF41H) Register Address Comment ∗1 Name Init High High FF30H P40–P43 I/O port data High High IOC43 Output Input IOC43 IOC42 IOC41 IOC40 IOC42 Output Input FF31H P40–P43 I/O control register IOC41 Output Input...
  • Page 29 SIC63616-(Rev. 1.0) NO. P22 Table 4.1.1 (f) I/O memory map (FF42H-FF51H) Register Address Comment ∗1 Name Init Clock timer data (1 Hz) Clock timer data (2 Hz) FF42H Clock timer data (4 Hz) Clock timer data (8 Hz) ENRTM 1 sec 0.5 sec Envelope releasing time selection ENRTM ENRST ENON...
  • Page 30 SIC63616-(Rev. 1.0) NO. P23 Table 4.1.1 (g) I/O memory map (FF52H-FF67H) Register Address Comment ∗1 Name Init LCD contrast adjustment [LC3–0] – FF52H Contrast Light – Dark ∗3 ∗2 – Unused ESOUT SCTRG ESIF ESOUT Enable Disable SOUT enable FF58H SCTRG Trigger Invalid...
  • Page 31 SIC63616-(Rev. 1.0) NO. P24 Table 4.1.1 (h) I/O memory map (FF68H-FF82H) Register Address Comment ∗1 Name Init ∗2 – ∗2 – FF68H Time base counter TC4–TC7 ∗2 – ∗2 – ∗2 TC11 – TC11 TC10 ∗2 TC10 – FF69H Time base counter TC8–TC11 ∗2 –...
  • Page 32 SIC63616-(Rev. 1.0) NO. P25 Table 4.1.1 (i) I/O memory map (FF84H-FF91H) Register Address Comment ∗1 Name Init RLD03 RLD03 RLD02 RLD01 RLD00 RLD02 FF84H Programmable timer 0 reload data (low-order 4 bits) RLD01 RLD00 RLD07 RLD07 RLD06 RLD05 RLD04 RLD06 FF85H Programmable timer 0 reload data (high-order 4 bits) RLD05...
  • Page 33 SIC63616-(Rev. 1.0) NO. P26 Table 4.1.1 (j) I/O memory map (FF92H-FFA0H) Register Address Comment ∗1 Name Init ∗3 ∗2 PTRST3 – Reset Invalid Programmable timer 3 reset (reload) PTRST3 PTRUN3 PTRST2 PTRUN2 PTRUN3 Stop Programmable timer 3 Run/Stop FF92H ∗3 ∗2 PTRST2 –...
  • Page 34 SIC63616-(Rev. 1.0) NO. P27 Table 4.1.1 (k) I/O memory map (FFA1H-FFAFH) Register Address Comment ∗1 Name Init PTSEL5 Normal Programmable timer 5 PWM output selection PTSEL5 PTSEL4 CHSEL_C PTOUT_C PTSEL4 Normal Programmable timer 4 PWM output selection FFA1H CHSEL_C General-purpose register PTOUT_C General-purpose register ∗3...
  • Page 35 SIC63616-(Rev. 1.0) NO. P28 Table 4.1.1 (l) I/O memory map (FFB0H-FFBEH) Register Address Comment ∗1 Name Init MOD16_D 16 bits 8 bits PTM6–7 16-bit mode selection MOD16_D EVCNT_D FCSEL_D PLPUL_D EVCNT_D Event ct. Timer PTM6 counter mode selection FFB0H FCSEL_D With NR No NR PTM6 function selection (for event counter mode)
  • Page 36 SIC63616-(Rev. 1.0) NO. P29 Table 4.1.1 (m) I/O memory map (FFBFH-FFEDH) Register Address Comment ∗1 Name Init CD77 CD77 CD76 CD75 CD74 CD76 FFBFH Programmable timer 7 compare data (high-order 4 bits) CD75 CD74 General General-purpose register General EIRFE EIRFR EIRFS EIRFE Enable Mask...
  • Page 37 SIC63616-(Rev. 1.0) NO. P30 Table 4.1.1 (n) I/O memory map (FFEEH-FFFCH) Register Address Comment ∗1 Name Init EIT3 Enable Mask Interrupt mask register (Clock timer 16 Hz) EIT3 EIT2 EIT1 EIT0 EIT2 Enable Mask Interrupt mask register (Clock timer 32 Hz) FFEEH EIT1 Enable...
  • Page 38 SIC63616-(Rev. 1.0) NO. P31 Table 4.1.1 (o) I/O memory map (FFFDH-FFFFH) Register Address Comment ∗1 Name Init IRUN Interrupt factor flag (Stopwatch direct RUN) IRUN ILAP ISW1 ISW10 ILAP Interrupt factor flag (Stopwatch direct LAP) FFFDH ISW1 Interrupt factor flag (Stopwatch timer 1 Hz) ISW10 Reset Invalid...

  • Page 39: Power Control

    4.2 Power Control 4.2.1 Configuration of power supply circuit The S1C63616 has built-in power supply circuits shown in Figure 4.2.1.1 so the voltages to drive the CPU, internal logic circuits, oscillation circuits and LCD driver can be generated on the chip.

  • Page 40: Controlling The Power Supply Voltage Booster/Halver And Voltage Regulators

    SIC63616-(Rev. 1.0) NO. P33 4.2.2 Controlling the power supply voltage booster/halver and voltage regulators Controlling the power supply voltage booster/halver The power supply voltage booster/halver generates the operating voltage V for driving the voltage regulator (LCD system voltage regulator) when the supply voltage V is out of their operating voltage range.

  • Page 41: Heavy Load Protection Function

    SIC63616-(Rev. 1.0) NO. P34 Table 4.2.2.1 lists settings of the above registers according to the supply voltage V Table 4.2.2.1 Power control register settings according to supply voltage V When V reference LCD drive power option is selected Power supply Power source for internal and Power source for LCD system DBON...
  • Page 42 SIC63616-(Rev. 1.0) NO. P35 HLON: Power supply voltage booster/halver halving mode On/Off register (FF02H•D1) Activates the power supply voltage booster/halver in halving mode. When "1" is written: Halver On When "0" is written: Halver Off Reading: Valid HLON is prohibited from use. Always be sure to set to "0". At initial reset, this register is set to "0".

  • Page 43: Programming Notes

    SIC63616-(Rev. 1.0) NO. P36 VCHLMOD: LCD system voltage regulator heavy load protection On/Off register (FF03H•D3) Enables heavy load protection function for the LCD system voltage regulator. When "1" is written: On When "0" is written: Off Reading: Valid By writing "1" to VCHLMOD, the LCD system voltage regulator enters heavy load protection mode to minimize degradation in display quality when fluctuations in the supply voltage occurs due to driving a heavy load.

  • Page 44: Watchdog Timer

    4.3.1 Configuration of watchdog timer The S1C63616 has a built-in watchdog timer that operates with a 256 Hz divided clock from the OSC1 as the source clock. The watchdog timer starts operating after initial reset, however, it can be stopped by the software.

  • Page 45: I/O Memory Of Watchdog Timer

    SIC63616-(Rev. 1.0) NO. P38 4.3.3 I/O memory of watchdog timer Table 4.3.3.1 shows the I/O address and control bits for the watchdog timer. Table 4.3.3.1 Control bits of watchdog timer Register Address Comment ∗1 Name Init ∗3 ∗2 – Unused WDEN WDRST ∗3 ∗2...

  • Page 46: Oscillation Circuit

    4.4 Oscillation Circuit 4.4.1 Configuration of oscillation circuit The S1C63616 is configured as a twin clock system with two internal oscillation circuits (OSC1 and OSC3). The OSC1 oscillation circuit generates the main-clock (Typ. 32.768 kHz) for low-power operation and the OSC3 oscillation circuit generates the sub-clock (Max.

  • Page 47: Osc1 Oscillation Circuit

    SIC63616-(Rev. 1.0) NO. P40 4.4.3 OSC1 oscillation circuit The OSC1 oscillation circuit generates the 32.768 kHz (Typ.) system clock which is used during low speed (low power) operation of the CPU and peripheral circuits. Furthermore, even when OSC3 is used as the system clock, OSC1 continues to generate the source clock for the clock timer and stopwatch timer.

  • Page 48: Switching The Cpu Clock

    SIC63616-(Rev. 1.0) NO. P41 4.4.5 Switching the CPU clock Either the OSC1 clock or the OSC3 clock can be selected as the CPU system clock using the CLKCHG register. The OSC3 oscillation circuit can be turned off (OSCC = "0") to save power while the CPU is operating with the OSC1 clock (CLKCHG = "0").

  • Page 49: I/O Memory Of Oscillation Circuit

    SIC63616-(Rev. 1.0) NO. P42 4.4.6 I/O memory of oscillation circuit Table 4.4.6.1 shows the I/O address and the control bits for the oscillation circuit. Note: The control bits for the oscillation circuit described below are effective only when the OSC3 oscil- lation circuit is used.

  • Page 50: Programming Notes

    Using a single instruction to process simultaneously can cause a malfunction of the CPU. (4) The S1C63616 supports the SLEEP function and both the OSC1 and OSC3 oscillation circuits stop oscil- lating when the CPU enters SLEEP mode. To prevent the CPU from a malfunction when it resumes operating from SLEEP mode, switch the CPU clock to OSC1 before placing the CPU into SLEEP mode.

  • Page 51: I/O Ports (P00-P03, P10-P13, P20-P23 And P40-P43)

    (P00-P03, P10-P13, P20-P23 and P40-P43) 4.5.1 Configuration of I/O ports The S1C63616 is equipped with 16 bits of I/O ports (P00–P03, P10–P13, P20–P23 and P40–P43) in which the input/output direction can be switched with software. Figure 4.5.1.1 shows the structure of an I/O port.

  • Page 52: Mask Option

    SIC63616-(Rev. 1.0) NO. P45 Table 4.5.1.1 Function setting of input/output terminals When special outputs/peripheral functions are used (selected by software) Terminal Terminal status Special output Serial I/F Stopwatch Event name at initial reset R/f converter TOUT FOUT Master Slave direct input counter P00 (Input &...

  • Page 53: I/O Control Registers And Input/Output Mode

    I/O port. 4.5.5 Pull-down during input mode A pull-down resistor that activates during the input mode can be built into the I/O ports of the S1C63616. The pull-down resistor becomes effective by writing "1" to the pull-down control register PULxx that corresponds to each port, and the input line is pulled down during input mode.

  • Page 54: Special Output

    TOUT output (P13) In order for the S1C63616 to provide clock signals to external devices, the P13 terminal can be used to output the TOUT_A signal (clocks output by the programmable timer).
  • Page 55 SIC63616-(Rev. 1.0) NO. P48 Table 4.5.6.2 FOUT frequency selection FOUT3 FOUT2 FOUT1 FOUT0 FOUT frequency OSC3 OSC3 OSC3 OSC3 / 16 OSC3 / 32 OSC3 / 64 OSC3 / 256 OSC3 (32 kHz) OSC1 (16 kHz) OSC1 (8 kHz) OSC1 / 16 (2 kHz) OSC1 / 32 (1 kHz)

  • Page 56: Key Input Interrupt Function

    SIC63616-(Rev. 1.0) NO. P49 4.5.7 Key input interrupt function Eight bits of the I/O ports (P10–P13, P40–P43) provide the interrupt function. The conditions for generating an interrupt can be set with software. Further, whether to mask the interrupt function can be selected with software.
  • Page 57 SIC63616-(Rev. 1.0) NO. P50 The interrupt select registers (SIP00–SIP03, SIP10–SIP13) and interrupt polarity select registers (PCP00– PCP03, PCP10–PCP13) are individually provided for the I/O ports P10–P13 and P40–P43. The interrupt select registers (SIPxx) select the ports to be used for generating interrupts or canceling SLEEP mode.

  • Page 58: I/O Memory Of I/O Ports

    SIC63616-(Rev. 1.0) NO. P51 4.5.8 I/O memory of I/O ports Table 4.5.8.1 shows the I/O addresses and the control bits for the I/O ports. Table 4.5.8.1(a) Control bits of I/O ports Register Address Comment ∗1 Name Init FOUT frequency selection FOUT3 [FOUT3–0] FOUT3 FOUT2 FOUT1 FOUT0...
  • Page 59 SIC63616-(Rev. 1.0) NO. P52 Table 4.5.8.1(b) Control bits of I/O ports Register Address Comment ∗1 Name Init P13 pull-down control register PUL13 PUL13 PUL12 PUL11 PUL10 functions as a general-purpose register when TOUT_A is used P12 pull-down control register FF26H PUL12 P11 pull-down control register PUL11...
  • Page 60 SIC63616-(Rev. 1.0) NO. P53 Table 4.5.8.1(c) Control bits of I/O ports Register Address Comment ∗1 Name Init High High FF30H P40–P43 I/O port data High High IOC43 Output Input IOC43 IOC42 IOC41 IOC40 IOC42 Output Input FF31H P40–P43 I/O control register IOC41 Output Input...
  • Page 61 SIC63616-(Rev. 1.0) NO. P54 Table 4.5.8.1(d) Control bits of I/O ports Register Address Comment ∗1 Name Init PCP03 PCP03 PCP02 PCP01 PCP00 PCP02 FF3DH P10–P13 interrupt polarity select register PCP01 PCP00 SIP13 Enable Disable SIP13 SIP12 SIP11 SIP10 SIP12 Enable Disable FF3EH P40–P43 interrupt select register...
  • Page 62 SIC63616-(Rev. 1.0) NO. P55 Table 4.5.8.1(e) Control bits of I/O ports Register Address Comment ∗1 Name Init Programmable timer 5 PWM output selection PTSEL5 Normal PTSEL5 PTSEL4 CHSEL_C PTOUT_C Programmable timer 4 PWM output selection PTSEL4 Normal FFA1H General-purpose register CHSEL_C General-purpose register PTOUT_C...
  • Page 63 SIC63616-(Rev. 1.0) NO. P56 ERF1, ERF0: R/f conversion select register (FF60H•D1, D0) Selects the function for P00–P03. When using the R/f converter, write "01B–11B" to this register and when P00–P03 are used as I/O ports, write "00B". Furthermore, when the RFOUT terminal is disabled (RFOUT = "0"), P03 can be used as an I/O port even if the R/f converter is used.
  • Page 64 SIC63616-(Rev. 1.0) NO. P57 • When reading data When "1" is read: High level When "0" is read: Low level When the I/O port is placed into input mode, the voltage level being input to the port terminal can be read out.
  • Page 65 SIC63616-(Rev. 1.0) NO. P58 These registers enable the built-in pull-down resistor to be effective during input mode in 1-bit units. (The pull-down resistor is included into the ports selected by mask option.) By writing "1" to the pull-down control register, the corresponding I/O ports are pulled down during input mode, while writing "0"...
  • Page 66 SIC63616-(Rev. 1.0) NO. P59 NRSP01, NRSP00: Key input interrupt 0–3 noise reject frequency select register (FF11H•D1, D0) NRSP11, NRSP10: Key input interrupt 4–7 noise reject frequency select register (FF11H•D3, D2) Selects the noise reject frequency for the key input interrupts. Table 4.5.8.2 Setting up noise rejector NRSP01 NRSP00...
  • Page 67 SIC63616-(Rev. 1.0) NO. P60 (3) Special output control FOUT0–FOUT3: FOUT frequency select register (FF10H) Selects the frequency of the FOUT signal and controls the FOUT output. Table 4.5.8.3 FOUT clock frequency FOUT3 FOUT2 FOUT1 FOUT0 FOUT frequency OSC3 OSC3 OSC3 OSC3 / 16 OSC3...

  • Page 68: Programming Notes

    SIC63616-(Rev. 1.0) NO. P61 PTOUT_A: TOUT_A output control register (FF81H•D0) Controls the TOUT_A output. When "1" is written: TOUT output On When "0" is written: TOUT output Off Reading: Valid By writing "1" to the PTOUT_A register, the TOUT_A signal is output from the P13 terminal. When "0" is written, the corresponding terminal is used as a general-purpose DC input/output port.

  • Page 69: Lcd Driver

    4.6.1 Configuration of LCD driver The S1C63616 has a built-in dot matrix LCD driver that can drive an LCD panel with a maximum of 1,280 dots (40 segments × 32 commons). Figures 4.6.1.1 to 4.6.1.3 show the configuration of the LCD driver and the drive power supply.

  • Page 70: Power Supply For Lcd Driving

    Fig. 4.6.1.3 Configuration of LCD driver and drive power supply (V reference, 1/4 bias) 4.6.2 Power supply for LCD driving (1) Mask option The S1C63616 provides three options to configure the internal LCD power supply for generating the LCD drive voltages V –V TYPE 1 reference, 1/5 bias = 1.6 to 2.5 V (power supply voltage booster/halver is used)
  • Page 71 SIC63616-(Rev. 1.0) NO. P64 (2) Controlling the LCD system voltage regulator To start LCD display, turn the LCD system voltage regulator on using the LPWR register. When "1" is written to LPWR, the LCD system voltage regulator goes on and generates the LCD drive voltages listed in Table 4.6.2.1.

  • Page 72: Controlling Lcd Display

    The contents in the display RAM are not modified. (2) Drive duty and frame frequency The S1C63616 supports three types of LCD drive duty settings, 1/32, 1/24 and 1/16, and can be switched using the LDUTY2–LDUTY0 register as shown in Table 4.6.3.2. Select an appropriate drive duty according to the LCD panel to be used.
  • Page 73 SIC63616-(Rev. 1.0) NO. P66 32 Hz – – – – COM0 COM0 COM1 COM2 SEG0 SEG1 COM0–SEG0 (GND) (GND) COM0–SEG1 Fig. 4.6.3.1 Drive waveform for 1/32 duty (FLCKS = "00B") 3240-0412...
  • Page 74 SIC63616-(Rev. 1.0) NO. P67 42 (21) Hz – – – – COM0 COM0 COM1 COM2 SEG0 SEG1 COM0–SEG0 (GND) (GND) COM0–SEG1 Fig. 4.6.3.2 Drive waveform for 1/24 duty (FLCKS = "00B") 3240-0412...
  • Page 75 SIC63616-(Rev. 1.0) NO. P68 32 Hz – – – – COM0 COM0 COM1 COM2 SEG0 SEG1 (GND) COM0–SEG0 (GND) COM0–SEG1 Fig. 4.6.3.3 Drive waveform for 1/16 duty (FLCKS = "00B") 3240-0412...

  • Page 76: Display Memory

    SIC63616-(Rev. 1.0) NO. P69 4.6.4 Display memory The display memory is allocated to F000H–F36FH in the data memory area and the addresses and the data bits correspond to COM and SEG outputs as shown in Figures 4.6.4.1 to 4.6.4.3. SEG0 SEG1 SEG2 SEG3...
  • Page 77 SIC63616-(Rev. 1.0) NO. P70 SEG0 SEG1 SEG2 SEG3 SEG47 COM0 ■ ■ ■ ■ ■ COM1 ■ ■ ■ ■ ■ F000H F002H F004H F006H ..F05EH COM2 ■ ■ ■ ■ ■ COM3 ■ ■ ■...
  • Page 78 SIC63616-(Rev. 1.0) NO. P71 SEG0 SEG1 SEG2 SEG3 SEG55 COM0 ■ ■ ■ ■ ■ COM1 ■ ■ ■ ■ ■ F000H F002H F004H F006H ..F06EH COM2 ■ ■ ■ ■ ■ COM3 ■ ■ ■...

  • Page 79: Lcd Contrast Adjustment

    SIC63616-(Rev. 1.0) NO. P72 4.6.5 LCD contrast adjustment The LCD driver allows the software to adjust the LCD contrast. It is realized by controlling the voltages V –V output from the LCD system voltage regulator. The contrast can be adjusted to 16 levels using the LC3–LC0 register. Table 4.6.5.1 LCD contrast Contrast Light...

  • Page 80: I/O Memory Of Lcd Driver

    SIC63616-(Rev. 1.0) NO. P73 4.6.6 I/O memory of LCD driver Table 4.6.6.1 shows the I/O addresses and the control bits for the LCD driver. Figure 4.6.6.1 shows the display memory map. Table 4.6.6.1 Control bits of LCD driver Register Address Comment ∗1 Name Init...
  • Page 81 SIC63616-(Rev. 1.0) NO. P74 1/32 duty 1/24 duty 1/16 duty F000H SEG0 SEG0 SEG0 Display data area Display data area (COM0–COM7) F04FH SEG39 (COM0–COM7) Display data area 0 F050H (COM0–COM7) F05FH SEG47 Unused area F060H Unused area F06FH SEG55 F070H Not implemented Not implemented Not implemented...
  • Page 82 SIC63616-(Rev. 1.0) NO. P75 DBON: Power supply voltage booster/halver boost mode On/Off register (FF02H•D0) Activates the power supply voltage booster/halver in boost mode. When "1" is written: Booster On When "0" is written: Booster Off Reading: Valid When "1" is written to DBON, the power supply voltage booster/halver activates in boost mode and almost doubles the V voltage to generate the V voltage.
  • Page 83 SIC63616-(Rev. 1.0) NO. P76 VCCKS0, VCCKS1: VC boost frequency select register (FF12H•D0, D1) Controls the boost clock supply to the LCD system voltage regulator. Table 4.6.6.2 Controlling boost clock VCCKS1 VCCKS0 Boost clock control Prohibited On (2 kHz) The LCD system voltage regulator uses the boost clock supplied from the clock manager for boosting/ reducing the voltage.
  • Page 84 SIC63616-(Rev. 1.0) NO. P77 LDUTY0–LDUTY2: LCD drive duty switching register (FF51H•D0–D2) Selects the LCD drive duty. Table 4.6.6.5 Drive duty setting Frame frequency Drive bias LDUTY2 LDUTY1 LDUTY0 Duty FLCKS = 11B FLCKS = 10B FLCKS = 01B FLCKS = 00B (mask option) Prohibited –...

  • Page 85: Programming Notes

    SIC63616-(Rev. 1.0) NO. P78 4.6.7 Programming notes (1) When a program that access no memory implemented area (F070H–F0FFH, F170H–F1FFH, F270H– F2FFH, F370H–F3FFH) is made, the operation is not guaranteed. (2) When driving the LCD system voltage regulator with V , wait at least 1 msec for stabilization of the voltage before switching the power voltage for the LCD system voltage regulator to V using VCSEL after the power supply voltage booster/halver is turned on.

  • Page 86: Clock Timer

    4.7 Clock Timer 4.7.1 Configuration of clock timer The S1C63616 has a built-in clock timer that uses OSC1 (crystal oscillator) as the source oscillator. The clock timer is configured of an 8-bit binary counter that serves as the input clock, f...

  • Page 87: Interrupt Function

    SIC63616-(Rev. 1.0) NO. P80 4.7.4 Interrupt function The clock timer can generate an interrupt at the falling edge of 128 Hz, 64 Hz, 32 Hz, 16 Hz, 8 Hz, 4 Hz, 2 Hz and 1 Hz signals. Software can enable or mask any of these frequencies to generate interrupts. Figure 4.7.4.1 is the timing chart of the clock timer.

  • Page 88: I/O Memory Of Clock Timer

    SIC63616-(Rev. 1.0) NO. P81 4.7.5 I/O memory of clock timer Table 4.7.5.1 shows the I/O addresses and the control bits for the clock timer. Table 4.7.5.1 Control bits of clock timer Register Address Comment ∗1 Name Init MDCKE Enable Disable Integer multiplier clock enable MDCKE SGCKE SWCKE RTCKE SGCKE...
  • Page 89 SIC63616-(Rev. 1.0) NO. P82 TMRUN: Clock timer Run/Stop control register (FF40H•D0) Controls run/stop of the clock timer. When "1" is written: Run When "0" is written: Stop Reading: Valid The clock timer starts running when "1" is written to the TMRUN register, and stops when "0" is written. In stop status, the timer data is maintained until the next run status or the timer is reset.

  • Page 90: Programming Notes

    SIC63616-(Rev. 1.0) NO. P83 IT0: 128 Hz interrupt factor flag (FFFEH•D0) IT1: 64 Hz interrupt factor flag (FFFEH•D1) IT2: 32 Hz interrupt factor flag (FFFEH•D2) IT3: 16 Hz interrupt factor flag (FFFEH•D3) IT4: 8 Hz interrupt factor flag (FFFFH•D0) IT5: 4 Hz interrupt factor flag (FFFFH•D1) IT6: 2 Hz interrupt factor flag (FFFFH•D2)

  • Page 91: Stopwatch Timer

    4.8.1 Configuration of stopwatch timer The S1C63616 has a 1/1,000 sec stopwatch timer. The stopwatch timer is configured of a 3-stage, 4-bit BCD counter serving as the input clock of a 1,000 Hz signal output from the prescaler. Data can be read out four bits (1/1,000 sec, 1/100 sec and 1/10 sec) at a time by the software.

  • Page 92: Counter And Prescaler

    SIC63616-(Rev. 1.0) NO. P85 4.8.3 Counter and prescaler The stopwatch timer is configured of four-bit BCD counters SWD0–3, SWD4–7 and SWD8–11. The counter SWD0–3, at the stage preceding the stopwatch timer, has a 1,000 Hz signal generated by the prescaler for the input clock. It counts up every 1/1,000 sec, and generates 100 Hz signal. The counter SWD4–7 has a 100 Hz signal generated by the counter SWD0–3 for the input clock.

  • Page 93: Stopwatch Timer Run/Stop And Reset

    SIC63616-(Rev. 1.0) NO. P86 Direct LAP input (P11/P10) Direct LAP internal signal Capture renewal flag CRNWF SWD0–3 reading SWD4–7 reading SWD8–11 reading Data holding Fig. 4.8.4.1 Timing for data holding and reading 4.8.5 Stopwatch timer RUN/STOP and reset RUN/STOP control and reset of the stopwatch timer can be done by the software. Stopwatch timer RUN/STOP The stopwatch timer enters the RUN status when "1"...

  • Page 94: Direct Input Function And Key Mask

    SIC63616-(Rev. 1.0) NO. P87 4.8.6 Direct input function and key mask The stopwatch timer has a direct input function that can control the RUN/STOP and LAP operation of the stopwatch timer by external key input. This function is set by writing "1" to the EDIR register. When EDIR is set to "0", only the software control is possible as explained in the previous section.
  • Page 95 SIC63616-(Rev. 1.0) NO. P88 The stopwatch timer sets the 1 Hz interrupt factor flag ISW1 to "1" when requiring a carry-up to 1-sec digit by an SWD8–11 overflow. If the capture buffer shifts into hold status (when SWD0–3 is read or when LAP is input) while the 1 Hz interrupt factor flag ISW1 is set to "1", the lap data carry-up request flag LCURF is set to "1"...
  • Page 96 SIC63616-(Rev. 1.0) NO. P89 RUN or LAP inputs become invalid in the following status. 1. The RUN or LAP key is pressed when one or more keys that are included in the selected combina- tion (here in after referred to as mask) are held down. 2.

  • Page 97: Interrupt Function

    SIC63616-(Rev. 1.0) NO. P90 4.8.7 Interrupt function 10 Hz and 1 Hz interrupts The 10 Hz and 1 Hz interrupts can be generated through the overflow of stopwatch timers SWD4–7 and SWD8–11 respectively. Also, software can set whether to separately mask the frequencies described earlier.
  • Page 98 SIC63616-(Rev. 1.0) NO. P91 Direct RUN and direct LAP interrupts When the direct input function is selected, the direct RUN and direct LAP interrupts can be generated. The respective interrupts occur at the rising edge of the internal signal for direct RUN and direct LAP after sampling the direct input signal in the falling edge of 1,024 Hz signal.

  • Page 99: I/O Memory Of Stopwatch Timer

    SIC63616-(Rev. 1.0) NO. P92 4.8.8 I/O memory of stopwatch timer Table 4.8.8.1 shows the I/O addresses and the control bits for the stopwatch timer. Table 4.8.8.1 Control bits of stopwatch timer Register Address Comment ∗1 Name Init MDCKE Enable Disable Integer multiplier clock enable MDCKE SGCKE SWCKE RTCKE SGCKE...
  • Page 100 SIC63616-(Rev. 1.0) NO. P93 EDIR: Direct input function enable register (FF48H•D0) Enables the direct input (RUN/LAP) function. When "1" is written: Enabled When "0" is written: Disabled Reading: Valid The direct input function is enabled by writing "1" to EDIR, and then RUN/STOP and LAP control can be done by external key input.
  • Page 101 SIC63616-(Rev. 1.0) NO. P94 SWRUN: Stopwatch timer RUN/STOP (FF4AH•D1) This register controls the RUN/STOP of the stopwatch timer, and the operating status can be monitored by reading this register. • When writing data When "1" is written: RUN When "0" is written: STOP The stopwatch timer enters the RUN status when "1"...
  • Page 102 SIC63616-(Rev. 1.0) NO. P95 SWD4–SWD7: Stopwatch timer data 1/100 sec (FF4CH) Data (BCD) of the 1/100 sec column of the capture buffer can be read out. These 4 bits are read-only, and cannot be used for writing operations. At initial reset, the timer data is set to "0". SWD8–SWD11: Stopwatch timer data 1/10 sec (FF4DH) Data (BCD) of the 1/10 sec column of the capture buffer can be read out.

  • Page 103: Programming Notes

    SIC63616-(Rev. 1.0) NO. P96 4.8.9 Programming notes (1) The interrupt factor flag should be reset after resetting the stopwatch timer. (2) Be sure to data reading in the order of SWD0–3 → SWD4–7 → SWD8–11. (3) When data that is held by a LAP input is read, read the capture buffer renewal flag CRNWF after read- ing the SWD8–11 and check whether the data has been renewed or not.

  • Page 104: Programmable Timer

    4.9 Programmable Timer 4.9.1 Configuration of programmable timer The S1C63616 has built-in four (Ch.A–Ch.D) units of 8 bits × 2-channel programmable timers. Each unit may be configured to 8-bit timer × 2 channels or 16-bit timer × 1 channel with software.
  • Page 105 SIC63616-(Rev. 1.0) NO. P98 Timer 2 Reload data register P41 port Timer 2 reset PTRST2 RLD20–RLD27 Timer 2 PTRUN2 Run/Stop 8-bit down counter Timer Timer 2 clock control circuit Timer function setting FCSEL_B Data buffer Comparator PTPS20–PTPS23 Pulse polarity setting PLPUL_B PTD20–PTD27 Timer 2 clock selection...
  • Page 106 SIC63616-(Rev. 1.0) NO. P99 Timer 6 Reload data register P43 port Timer 6 reset PTRST6 RLD60–RLD67 Timer 6 PTRUN6 Run/Stop 8-bit down counter Timer Timer 6 control clock circuit Timer function setting FCSEL_D Data buffer Comparator PTPS60–PTPS63 Pulse polarity setting PLPUL_D PTD60–PTD67 Timer 6 clock selection...

  • Page 107: Controlling Clock Manager

    SIC63616-(Rev. 1.0) NO. P100 4.9.2 Controlling clock manager The clock manager generates the down-count clock for each timer by dividing the OSC1 or OSC3 clock. Table 4.9.2.1 lists the 15 count clocks that can be generated by the clock manager, and the clock to be used for each timer can be selected using the count clock frequency select register PTPSx0–PTPSx3.

  • Page 108: Basic Count Operation

    SIC63616-(Rev. 1.0) NO. P101 4.9.3 Basic count operation This section explains the basic count operation when each timer is used as an individual 8-bit timer. Each timer has an 8-bit down counter and an 8-bit reload data register. The reload data register RLDx0–RLDx7 is used to set the initial value to the down counter. By writing "1"...

  • Page 109: Event Counter Mode (Timers 0, 2, 4 And 6)

    SIC63616-(Rev. 1.0) NO. P102 4.9.4 Event counter mode (Timers 0, 2, 4 and 6) Timer 0 has an event counter function that counts an external clock input to an I/O port. Table 4.9.4.1 lists the timers and their clock input ports. Table 4.9.4.1 Event counter clock input port Timer External clock name...

  • Page 110: Pwm Mode (Timers 0-7)

    SIC63616-(Rev. 1.0) NO. P103 4.9.5 PWM mode (Timers 0-7) Each timer can generate a PWM waveform. When using this function, write "1" to the PTSELx register to set the timer to PWM mode. The compare data register CDx0–CDx7 is provided for each timer to control the PWM waveform. In PWM mode, the timer compares data between the down counter and the compare data register and outputs the compare match signal if their contents are matched.

  • Page 111: Bit Timer Mode (Timer 0 + 1, Timer 2 + 3, Timer 4 + 5, Timer 6 + 7)

    SIC63616-(Rev. 1.0) NO. P104 4.9.6 16-bit timer mode (Timer 0 + 1, Timer 2 + 3, Timer 4 + 5, Timer 6 + 7) Timers 0 and 1, Timers 2 and 3, Timers 4 and 5, and Timers 6 and 7 combinations can be used as 16-bit timers.

  • Page 112: Interrupt Function

    SIC63616-(Rev. 1.0) NO. P105 4.9.7 Interrupt function The programmable timer can generate interrupts from the underflow and compare match signals of each timer. See Figures 4.9.3.1 and 4.9.5.1 for the interrupt timing. Note: The compare match interrupt can be generated only when the timer is set to PWM mode. The underflow and compare match signals set the corresponding interrupt factor flag IPTx and ICTCx to "1", and an interrupt is generated.

  • Page 113: Clock Output To Serial Interface And R/F Converter

    SIC63616-(Rev. 1.0) NO. P106 4.9.9 Clock output to serial interface and R/f converter The signal that is made from underflows of Timer 1 by dividing them by 2, can be used as the clock source for the serial interface and R/f converter. Timer 1 always outputs the clock to the serial interface and R/f converter by setting Timer 1 into RUN state (PTRUN1 = "1").

  • Page 114: I/O Memory Of Programmable Timer

    SIC63616-(Rev. 1.0) NO. P107 4.9.10 I/O memory of programmable timer Table 4.9.10.1 shows the I/O addresses and the control bits for the programmable timer. Table 4.9.10.1(a) Control bits of programmable timer Register Address Comment ∗1 Name Init PTPS03 Programmable timer 0 count clock frequency selection [PTPS03–00] PTPS03 PTPS02 PTPS01 PTPS00 PTPS02...
  • Page 115 SIC63616-(Rev. 1.0) NO. P108 Table 4.9.10.1(b) Control bits of programmable timer Register Address Comment ∗1 Name Init MOD16_A 16 bits 8 bits PTM0–1 16-bit mode selection MOD16_A EVCNT_A FCSEL_A PLPUL_A EVCNT_A Event ct. Timer PTM0 counter mode selection FF80H FCSEL_A With NR No NR PTM0 function selection (for event counter mode)
  • Page 116 SIC63616-(Rev. 1.0) NO. P109 Table 4.9.10.1(c) Control bits of programmable timer Register Address Comment ∗1 Name Init MOD16_B 16 bits 8 bits PTM2–3 16-bit mode selection MOD16_B EVCNT_B FCSEL_B PLPUL_B EVCNT_B Event ct. Timer PTM2 counter mode selection FF90H FCSEL_B With NR No NR PTM2 function selection (for event counter mode)
  • Page 117 SIC63616-(Rev. 1.0) NO. P110 Table 4.9.10.1(d) Control bits of programmable timer Register Address Comment ∗1 Name Init MOD16_C 16 bits 8 bits PTM4–5 16-bit mode selection MOD16_C EVCNT_C FCSEL_C PLPUL_C EVCNT_C Event ct. Timer PTM4 counter mode selection FFA0H FCSEL_C With NR No NR PTM4 function selection (for event counter mode)
  • Page 118 SIC63616-(Rev. 1.0) NO. P111 Table 4.9.10.1(e) Control bits of programmable timer Register Address Comment ∗1 Name Init MOD16_D 16 bits 8 bits PTM6–7 16-bit mode selection MOD16_D EVCNT_D FCSEL_D PLPUL_D EVCNT_D Event ct. Timer PTM6 counter mode selection FFB0H FCSEL_D With NR No NR PTM6 function selection (for event counter mode)
  • Page 119 SIC63616-(Rev. 1.0) NO. P112 Table 4.9.10.1(f) Control bits of programmable timer Register Address Comment ∗1 Name Init General General-purpose register General General EIPT0 EICTC0 General General-purpose register FFE2H EIPT0 Enable Mask Interrupt mask register (Programmable timer 0 underflow) EICTC0 Enable Mask Interrupt mask register (Programmable timer 0 compare match) General...
  • Page 120 SIC63616-(Rev. 1.0) NO. P113 Table 4.9.10.1(g) Control bits of programmable timer Register Address Comment ∗1 Name Init ∗3 ∗2 – Unused IPT6 ICTC6 ∗3 ∗2 – Unused FFF8H IPT6 Interrupt factor flag (Programmable timer 6 underflow) ICTC6 Reset Invalid Interrupt factor flag (Programmable timer 6 compare match) ∗3 ∗2 –...
  • Page 121 SIC63616-(Rev. 1.0) NO. P114 PLPUL_A: Timer 0 pulse polarity select register (FF80H•D0) PLPUL_B: Timer 2 pulse polarity select register (FF90H•D0) PLPUL_C: Timer 4 pulse polarity select register (FFA0H•D0) PLPUL_D: Timer 6 pulse polarity select register (FFB0H•D0) Selects the count pulse polarity in the event counter mode. When "1"...
  • Page 122 SIC63616-(Rev. 1.0) NO. P115 MOD16_A: Timer 0–1 16-bit timer mode select register (FF80H•D3) MOD16_B: Timer 2–3 16-bit timer mode select register (FF90H•D3) MOD16_C: Timer 4–5 16-bit timer mode select register (FFA0H•D3) MOD16_D: Timer 6–7 16-bit timer mode select register (FFB0H•D3) Selects 8-bit or 16-bit timer mode.
  • Page 123 SIC63616-(Rev. 1.0) NO. P116 PTSEL0: Timer 0 PWM mode select register (FF81H•D2) PTSEL1: Timer 1 PWM mode select register (FF81H•D3) PTSEL2: Timer 2 PWM mode select register (FF91H•D2) PTSEL3: Timer 3 PWM mode select register (FF91H•D3) PTSEL4: Timer 4 PWM mode select register (FFA1H•D2) PTSEL5: Timer 5 PWM mode select register (FFA1H•D3) PTSEL6: Timer 6 PWM mode select register (FFB1H•D2) PTSEL7: Timer 7 PWM mode select register (FFB1H•D3)
  • Page 124 SIC63616-(Rev. 1.0) NO. P117 The PTRSTx registers are all effective even in 16-bit timer mode, and reload data must be preset to both the high-order timer (Timer 1/3/5/7) and the low-order timer (Timer 0/2/4/6) separately. Since these bits are exclusively for writing, always set to "0" during reading. RLD00–RLD07: Timer 0 reload data register (FF84H, FF85H) RLD10–RLD17: Timer 1 reload data register (FF86H, FF87H) RLD20–RLD27: Timer 2 reload data register (FF94H, FF95H)
  • Page 125 SIC63616-(Rev. 1.0) NO. P118 EIPT0, EICTC0: Timer 0 interrupt mask registers (FFE2H•D1, D0) EIPT1, EICTC1: Timer 1 interrupt mask registers (FFE3H•D1, D0) EIPT2, EICTC2: Timer 2 interrupt mask registers (FFE4H•D1, D0) EIPT3, EICTC3: Timer 3 interrupt mask registers (FFE5H•D1, D0) EIPT4, EICTC4: Timer 4 interrupt mask registers (FFE6H•D1, D0) EIPT5, EICTC5: Timer 5 interrupt mask registers (FFE7H•D1, D0) EIPT6, EICTC6: Timer 6 interrupt mask registers (FFE8H•D1, D0)

  • Page 126: Programming Notes

    SIC63616-(Rev. 1.0) NO. P119 4.9.11 Programming notes (1) When reading counter data, be sure to read the low-order 4 bits (PTDx0–PTDx3) first. The high-order 4 bits (PTDx4–PTDx7) are latched when the low-order 4 bits are read and they are held until the next reading of the low-order 4 bits.
  • Page 127 SIC63616-(Rev. 1.0) NO. P120 (6) For the reason below, pay attention to the reload data write timing when changing the interval of the programmable timer interrupts while the programmable timer is running. The programmable timer counts down at the falling edge of the input clock and at the same time it gen- erates an interrupt if the counter underflows.

  • Page 128: Serial Interface

    The synchronous clock for serial data input/output may be set by selecting by software any one of seven types of master mode (internal clock mode: when the S1C63616 is to be the master for serial input/output) and a type of slave mode (external clock mode: when the S1C63616 is to be the slave for serial input/ output).

  • Page 129: Mask Option

    SIC63616-(Rev. 1.0) NO. P122 The serial interface input/output ports are shared with the I/O port (P20–P23), and they are configured to the I/O port terminals at initial reset. When using these terminals for the serial interface, switch the function with software as described above. At least ESIF must be set to 1. The switch operation automatically sets the input/output direction of the terminals.

  • Page 130: Operating Mode Of Serial Interface

    I/O port (in output mode) with software. Slave mode Slave mode is provided to use the S1C63616 as a slave device for serial transfer. In this mode, the serial interface inputs the synchronous clock that is sent by the external master device from the SCLK terminal to perform serial transfer.

  • Page 131: Setting Synchronous Clock

    SIC63616-(Rev. 1.0) NO. P124 Table 4.10.4.1 Mode settings and configurations of serial interface terminals ESIF SMOD ENCS ESREADY ESOUT Mode P20 terminal P21 terminal P22 terminal P23 terminal Prohibited Master mode SCLK (O) SOUT (O) SIN (I) P23 (I/O) SCLK (O) SOUT (O) SIN (I) P23 (I/O)

  • Page 132: Data Input/Output And Interrupt Function

    Serial data output procedure and interrupt The S1C63616 serial interface is capable of outputting parallel data as serial data, in units of 8 bits. By setting the parallel data to the data registers SD0–SD3 and SD4–SD7 and writing "1" to SCTRG bit, it synchronizes with the synchronous clock and the serial data is output to the SOUT (P21) terminal.
  • Page 133 Fig. 4.10.6.1 Serial data input/output permutation SRDY signal When the S1C63616 serial interface is used in the slave mode, the SRDY signal is used to indicate wheth- er the internal serial interface is ready to transmit or receive data for the master side (external) serial device.
  • Page 134 SIC63616-(Rev. 1.0) NO. P127 Timing chart The S1C63616 serial interface timing charts are shown in Figures 4.10.6.2 . SCTRG (W) SCTRG (R) SCLK 8-bit shift register SOUT ISIF SRDY (Slave mode) (a) When SCPS1 = "0" and SCPS0="0" SCTRG (W)

  • Page 135: Data Transfer In Spi Mode

    Section 4.10.6, "Data input/output and interrupt function", for these common descriptions. SPI slave device When using the S1C63616 as an SPI slave device, set the serial interface to SPI slave mode. ESIF = "1", SMOD = "0", ENCS = "1", ESREADY = "0", ESOUT = "1" (when SOUT is used) The P23 terminal functions as the SS (Slave Select) signal input terminal.

  • Page 136: I/O Memory Of Serial Interface

    SIC63616-(Rev. 1.0) NO. P129 4.10.8 I/O memory of serial interface Table 4.10.8.1 shows the I/O addresses and the control bits for the serial interface. Table 4.10.8.1 Control bits of serial interface Register Address Comment ∗1 Name Init General General-purpose register General SIFCKS2 SIFCKS1 SIFCKS0 [SIFCKS2–0] SIFCKS2...
  • Page 137 SIC63616-(Rev. 1.0) NO. P130 SIFCKS0–SIFCKS2: Serial interface clock frequency select register (FF14H•D0–D2) Selects the synchronous clock frequency in master mode. Table 4.10.8.2 Serial interface clock frequencies SIFCKS2 SIFCKS1 SIFCKS0 SIF clock (master mode) / 4 * OSC3 / 2 * OSC3 / 1 * OSC3...
  • Page 138 SIC63616-(Rev. 1.0) NO. P131 ESIF: Serial interface enable register (P2 port function selection) (FF58H•D0) Sets P20–P23 to the input/output port for the serial interface. When "1" is written: Serial interface When "0" is written: I/O port Reading: Valid When "1" is written to the ESIF register, P20, P21, P22 and P23 function as SIN, SOUT, SCLK and SRDY or SS, respectively.
  • Page 139 SIC63616-(Rev. 1.0) NO. P132 In master mode, the serial interface uses the internal clock (selected in the clock manager) as the synchronous clock for serial transfer. The synchronous clock is also output from the SCLK (P20) terminal to control the external serial interface (slave device). In slave mode, the serial interface inputs the synchronous clock that is sent by the external serial interface (master device) from the SCLK terminal to perform serial transfer.
  • Page 140 SIC63616-(Rev. 1.0) NO. P133 ESREADY: P23 port function select register (FF5AH•D1) Selects the P23 port function when ENCS = "1". When "1" is written: SRDY output When "0" is written: SS input Reading: Valid The P23 port function can be selected from SRDY output and SS input in slave mode (SMOD = "0"). At initial reset, this register is set to "0".

  • Page 141: Programming Notes

    SIC63616-(Rev. 1.0) NO. P134 ISIF: Interrupt factor flag (FFFAH•D0) This flag indicates the occurrence of serial interface interrupt. When "1" is read: Interrupt has occurred When "0" is read: Interrupt has not occurred When "1" is written: Flag reset When "0" is written: No operation From the status of this flag, the software can decide whether the serial interface interrupt.

  • Page 142: Sound Generator

    4.11 Sound Generator 4.11.1 Configuration of sound generator The S1C63616 has a built-in sound generator for generating a buzzer signal. Hence, the generated buzzer signal can be output from the BZ terminal. Aside permitting the respective setting of the buzzer signal frequency and sound level to 8 stages, it permits the adding of a digital envelope by means of duty ratio control.

  • Page 143: Setting Of Buzzer Frequency And Sound Level

    SIC63616-(Rev. 1.0) NO. P136 4.11.4 Setting of buzzer frequency and sound level The divided signal of the OSC1 oscillation clock (32.768 kHz) is used for the buzzer signal and it is set up such that 8 types of frequencies can be selected by changing this division ratio. Frequency selection is done by setting the buzzer frequency select register BZFQ0–BZFQ2 as shown in Table 4.11.4.1.

  • Page 144: Digital Envelope

    SIC63616-(Rev. 1.0) NO. P137 4.11.5 Digital envelope A digital envelope for duty control can be added to the buzzer signal. The envelope can be controlled by staged changing of the same duty envelope as detailed in Table 4.11.4.2 in the preceding item from level 1 (maximum) to level 8 (minimum). The addition of an envelope to the buzzer signal can be done by writing "1"...

  • Page 145: One-Shot Output

    SIC63616-(Rev. 1.0) NO. P138 4.11.6 One-shot output The sound generator has a one-shot output function for outputting a short duration buzzer signal for key operation sounds and similar effects. Either 125 msec or 31.25 msec can be selected by SHTPW register for one-shot buzzer signal output time.

  • Page 146: I/O Memory Of Sound Generator

    SIC63616-(Rev. 1.0) NO. P139 4.11.7 I/O memory of sound generator Table 4.11.7.1 shows the I/O addresses and the control bits for the sound generator. Table 4.11.7.1 Control bits of sound generator Register Address Comment ∗1 Name Init MDCKE Enable Disable Integer multiplier clock enable MDCKE SGCKE SWCKE RTCKE SGCKE...
  • Page 147 SIC63616-(Rev. 1.0) NO. P140 ENON: Envelope On/Off control register (FF44H•D1) Controls the addition of an envelope onto the buzzer signal. When "1" is written: On When "0" is written: Off Reading: Valid Writing "1" to ENON causes an envelope to be added during buzzer signal output. When a "0" has been written, an envelope is not added.
  • Page 148 SIC63616-(Rev. 1.0) NO. P141 • When reading When "1" is read: BUSY When "0" is read: READY During reading BZSHT shows the operation status of the one-shot output circuit. During one-shot output, BZSHT becomes "1" and the output goes off, it shifts to "0". At initial reset, this bit is set to "0".

  • Page 149: Programming Notes

    SIC63616-(Rev. 1.0) NO. P142 4.11.8 Programming notes (1) Since it generates a buzzer signal that is out of synchronization with the BZE register, hazards may at times be produced when the signal goes on/off due to the setting of the BZE register. (2) The one-shot output is only valid when the normal buzzer output is off (BZE = "0") and will be invalid when the normal buzzer output is on (BZE = "1").

  • Page 150: Integer Multiplier

    4.12 Integer Multiplier 4.12.1 Configuration of integer multiplier The S1C63616 has a built-in unsigned-integer multiplier. This multiplier performs 8 bits × 8 bits of multiplication or 16 bits ÷ 8 bits of division and returns the results and three flag states.

  • Page 151: Division Mode

    SIC63616-(Rev. 1.0) NO. P144 4.12.4 Division mode To perform a division, set the divisor to the source register (SR) and the dividend to the destination register (DRH and DRL), then write "1" to the calculation mode select register (CALMD). The division takes 10 CPU clock cycles from writing "1"...

  • Page 152: Execution Cycle

    SIC63616-(Rev. 1.0) NO. P145 4.12.5 Execution cycle Both the multiplication and division take 10 CPU cycles for an operation. Therefore, before the results can be read from the destination register DRH/DRL, wait at least 5 bus cycles after writing to CALMD. The same applies to reading the operation flags NF/VF/ZF.

  • Page 153: I/O Memory Of Integer Multiplier

    SIC63616-(Rev. 1.0) NO. P146 4.12.6 I/O memory of integer multiplier Table 4.12.6.1 shows the I/O addresses and the control bits for the integer multiplier. Table 4.12.6.1 Control bits of integer multiplier Register Address Comment ∗1 Name Init MDCKE Enable Disable Integer multiplier clock enable MDCKE SGCKE SWCKE RTCKE SGCKE...
  • Page 154 SIC63616-(Rev. 1.0) NO. P147 DRL0–DRL7: Destination register low-order 8 bits (FF72H, FF73H) Used to set multiplicands and low-order 8 bits of dividends. Set the low-order 4 bits of data to DRL0–DRL3 and the high-order 4 bits to DRL4–DRL7. Data written to this register is loaded to the arithmetic circuit when an operation starts (by writing to FF76H•D0), and then a multiplication or a division is performed in 10 CPU clock cycles (5 bus cycles).

  • Page 155: Programming Note

    SIC63616-(Rev. 1.0) NO. P148 NF: Negative flag (FF76H•D3) Indicates whether the operation result is a positive value or a negative value. When "1" is read: Negative value (MSB of the results is "1") When "0" is read: Positive value (MSB of the results is "0") Writing: Invalid NF is a read-only bit, so writing operation is invalid.

  • Page 156: R/F Converter

    4.13.1 Configuration of R/f converter The S1C63616 has a built-in CR oscillation type R/f converter that can be used as an A/D converter. Two systems (channel 0 and channel 1) of CR oscillation circuits are built into the R/f converter, so it is possible to compose two types of R/f conversion circuits by connecting different sensors to each CR oscillation circuit.

  • Page 157: Controlling Clock Manager

    SIC63616-(Rev. 1.0) NO. P150 4.13.2 Controlling clock manager The R/f converter uses the clock supplied from the clock manager as its operating clock and the count clock for the time base counter. The clock manager generates six R/f converter clocks by dividing the OSC1 and OSC3 clocks.
  • Page 158 SIC63616-(Rev. 1.0) NO. P151 Two systems of CR oscillation circuits, channel 0 and channel 1, are built into the R/f converter and perform CR oscillation with the external resistor and capacitor. The counter that is used to obtain R/f converted values is shared with channel 0 and channel 1. Therefore, operation for two channels is realized by switching the CR oscillation circuit that performs R/f conversion.

  • Page 159: Operation Of R/F Conversion

    SIC63616-(Rev. 1.0) NO. P152 (2) R/f conversion using an AC bias resistive sensor such as a humidity sensor This conversion is possible only in channel 1, and this method is selected by setting ERFx to "10B". This is basically the same as the R/f conversion described above (1), but the AC bias circuit works for a sen- sor (e.g.
  • Page 160 SIC63616-(Rev. 1.0) NO. P153 R/f conversion sequence An R/f conversion for the reference resistance starts by writing "1" to the RFRUNR register. However, an initial value must be set to the measurement counter and the time base counter must be cleared to "00000H"...

  • Page 161: Interrupt Function

    SIC63616-(Rev. 1.0) NO. P154 Since the reference resistance is oscillated until the measurement counter overflows, an appropriate initial value needs to be set before R/f conversion is started. If a smaller initial value is set, a longer counting period is possible, thereby ensuring more accurate detection. Convert the initial value into a complement (value subtracted from "00000H") before setting it on the measurement counter.
  • Page 162 SIC63616-(Rev. 1.0) NO. P155 R/f converter clock RFRUNR register Count-down Time base counter FFFFFH FFFFEH FFFFDH FFFFCH FFFFBH Measurement counter clock Measurement counter FFFFD FFFFEH FFFFFH Oscillation by reference resistance IRFR Interrupt request Fig. 4.13.5.1 Reference oscillate completion interrupt R/f converter clock RFRUNS register Count-up Time base counter...

  • Page 163: Continuous Oscillation Function

    SIC63616-(Rev. 1.0) NO. P156 4.13.6 Continuous oscillation function By setting the RFCNT register to "1", the reference oscillation or sensor oscillation can be continued even if the stop condition has been met. This function with RFOUT enabled allows easy measurement of the CR oscillation frequency.
  • Page 164 SIC63616-(Rev. 1.0) NO. P157 Register Address Comment ∗1 Name Init ∗2 TC15 – TC15 TC14 TC13 TC12 ∗2 TC14 – FF6AH Time base counter TC12–TC15 ∗2 TC13 – ∗2 TC12 – ∗2 TC19 – TC19 TC18 TC17 TC16 ∗2 TC18 –...
  • Page 165 SIC63616-(Rev. 1.0) NO. P158 RFOUT: RFOUT enable register (FF60H•D2) Enables RFOUT output from the P03 port. When "1" is written: Enabled (RFOUT) When "0" is written: Disabled (I/O port) Reading: Valid When using the RFOUT output, write "1" to RFOUT to set P03 as the RFOUT output port. At initial reset, this register is set to "0".
  • Page 166 SIC63616-(Rev. 1.0) NO. P159 OVMC: Measurement counter overflow flag (FF61H•D2) Indicates whether the measurement counter has overflown. When "1" is read: Overflow has occurred When "0" is read: Overflow has not occurred When "1" is written: Flag reset When "0" is written: No operation If an overflow occurs while counting the oscillation of the sensor, OVMC is set to "1"...

  • Page 167: Programming Notes

    SIC63616-(Rev. 1.0) NO. P160 EIRFS, EIRFR, EIRFE: Interrupt mask registers (FFE1H•D0–D2) Selects whether to mask interrupt with the R/f converter. When "1" is written: Enable When "0" is written: Mask Reading: Valid EIRFS, EIRFR and EIRFE are the interrupt mask registers for the sensor oscillate completion interrupt, reference oscillate completion interrupt and error interrupt.

  • Page 168: Svd (Supply Voltage Detection) Circuit

    4.14.1 Configuration of SVD circuit The S1C63616 has a built-in SVD (supply voltage detection) circuit, so that the software can find when the source voltage lowers. Turning the SVD circuit on/off and the SVD criteria voltage setting can be done with software.

  • Page 169: I/O Memory Of Svd Circuit

    SIC63616-(Rev. 1.0) NO. P162 4.14.3 I/O memory of SVD circuit Table 4.14.3.1 shows the I/O addresses and the control bits for the SVD circuit. Table 4.14.3.1 Control bits of SVD circuit Register Address Comment ∗1 Name Init SVD criteria voltage setting SVDS3 SVDS3 SVDS2 SVDS1 SVDS0 [SVDS3–0]...

  • Page 170: Interrupt And Halt/Sleep

    <HALT/SLEEP> The S1C63616 has the HALT and SLEEP functions that considerably reduce current consumption when it is not necessary. The CPU enters HALT status when the HALT instruction is executed. In HALT status, the operation of the CPU is stopped.
  • Page 171 SIC63616-(Rev. 1.0) NO. P164 5. Noise rejector selection register NRSPxx = "00" (noise rejector is bypassed) 6. Reset the Pxx input interrupt factor flag register (write “1” to the IKxx register) 7. Interrupt flag (I flag) = "1" (interrupts are enabled) 8-1.Confirm the input to the P1(4)x port is surely HIGH level when the P1(4)x port interrupt polarity select register = "1"...

  • Page 172: Interrupt Factor

    SIC63616-(Rev. 1.0) NO. P165 IRFE Watchdog timer NMI request EIRFE IRFR EIRFR IRFS EIRFS IPT0 EIPT0 ICTC0 EICTC0 IPT1 EIPT1 ICTC1 EICTC1 IPT2 EIPT2 ICTC2 EICTC2 IPT3 EIPT3 ICTC3 EICTC3 IPT4 EIPT4 ICTC4 EICTC4 IPT5 Interrupt Program EIPT5 vector counter ICTC5 generation (low-order 4 bits)
  • Page 173 SIC63616-(Rev. 1.0) NO. P166 4.15.1 Interrupt factor Table 4.15.1.1 shows the factors for generating interrupt requests. The interrupt flags are set to "1" depending on the corresponding interrupt factors. The CPU operation is interrupted when an interrupt factor flag is set to "1" if the following conditions are established.

  • Page 174: Interrupt Mask

    SIC63616-(Rev. 1.0) NO. P167 4.15.2 Interrupt mask The interrupt factor flags can be masked by the corresponding interrupt mask registers. The interrupt mask registers are read/write registers. They are enabled (interrupt authorized) when "1" is written to them, and masked (interrupt inhibited) when "0" is written to them. At initial reset, the interrupt mask register is reset to "0".

  • Page 175: Interrupt Vector

    SIC63616-(Rev. 1.0) NO. P168 4.15.3 Interrupt vector When an interrupt request is input to the CPU, the CPU begins interrupt processing. After the program being executed is terminated, the interrupt processing is executed in the following order. The content of the flag register is evacuated, then the I flag is reset. The address data (value of program counter) of the program to be executed next is saved in the stack area (RAM).
  • Page 176 SIC63616-(Rev. 1.0) NO. P169 ;****************************************************************************** subinterrupt vector area ;****************************************************************************** .org 0x120 INT_RFC: CALR INTRFC ;call Interrupt RFC RETI INT_DUMMY: RETI ;****************************************************************************** Interrupt RFC ;****************************************************************************** .org 0x800 INTRFC: %yl,P5CTL0@l %xl,ITC_RFC1@l [%y],[%x] ;Port Output 3240-0412...

  • Page 177: I/O Memory Of Interrupt

    SIC63616-(Rev. 1.0) NO. P170 4.15.4 I/O memory of interrupt Tables 4.15.4.1 shows the I/O addresses and the control bits for controlling interrupts. Table 4.15.4.1(a) Control bits of interrupt Register Address Comment ∗1 Name Init SIP03 Enable Disable SIP03 SIP02 SIP01 SIP00 SIP02 Enable...
  • Page 178 SIC63616-(Rev. 1.0) NO. P171 Table 4.15.4.1(b) Control bits of interrupt Register Address Comment ∗1 Name Init EIK03 Enable Mask Interrupt mask register (Key input interrupt 3 <P13>) EIK03 EIK02 EIK01 EIK00 EIK02 Enable Mask Interrupt mask register (Key input interrupt 2 <P12>) FFEBH EIK01 Enable...
  • Page 179 SIC63616-(Rev. 1.0) NO. P172 Table 4.15.4.1(c) Control bits of interrupt Register Address Comment ∗1 Name Init ∗3 ∗2 – Unused ISIF ∗3 ∗2 – Unused FFFAH ∗3 ∗2 – Unused ISIF Reset Invalid Interrupt factor flag (Serial interface) IK03 Interrupt factor flag (Key input interrupt 3 <P13>) IK03 IK02 IK01...

  • Page 180: Programming Notes

    SIC63616-(Rev. 1.0) NO. P173 EISIF: Interrupt mask register (FFEAH•D0) ISIF: Interrupt factor flag (FFFAH•D0) Refer to Section 4.10, "Serial Interface". EIRUN, EILAP, EISW1, EISW10: Interrupt mask registers (FFEDH) IRUN, ILAP, ISW1, ISW10: Interrupt factor flags (FFFDH) Refer to Section 4.8, "Stopwatch Timer". EIT3–EIT0, EIT7–EIT4: Interrupt mask registers (FFEEH, FFEFH) IT3–IT0, IT7–IT4: Interrupt factor flags (FFFEH, FFFFH) Refer to Section 4.7, "Clock Timer".

  • Page 181: Notes For Low Current Consumption

    5.1 Notes for Low Current Consumption The S1C63616 contains control registers for each of the circuits so that current consumption can be reduced. These control registers reduce the current consumption through programs that operate the circuits at the minimum levels.

  • Page 182: Summary Of Notes By Function

    00FFH. Therefore, pay attention to the SP1 value because it may be set to 0200H or more exceeding the 4-bit/16-bit accessible range in the S1C63616 or it may be set to 00FFH or less. Memory accesses ex- cept for stack operations by SP1 are 4-bit data access. After initial reset, all the interrupts including NMI are masked until both the stack pointers SP1 and SP2 are set by software.
  • Page 183 SIC63616-(Rev. 1.0) NO. P175 (4) The S1C63616 supports the SLEEP function and both the OSC1 and OSC3 oscillation circuits stop oscil- lating when the CPU enters SLEEP mode. To prevent the CPU from a malfunction when it resumes operating from SLEEP mode, switch the CPU clock to OSC1 before placing the CPU into SLEEP mode.
  • Page 184 SIC63616-(Rev. 1.0) NO. P176 Programmable timer (1) When reading counter data, be sure to read the low-order 4 bits (PTDx0–PTDx3) first. The high-order 4 bits (PTDx4–PTDx7) are latched when the low-order 4 bits are read and they are held until the next reading of the low-order 4 bits.
  • Page 185 SIC63616-(Rev. 1.0) NO. P177 To avoid improper reloading, do not rewrite the reload data after an interrupt occurs until the counter data is determined including the reloading period ➀ . Be especially careful when using the OSC1 (low- speed clock) as the clock source of the programmable timer and the CPU is operating with the OSC3 (high-speed clock).
  • Page 186 SIC63616-(Rev. 1.0) NO. P178 SVD circuit (1) To obtain a stable detection result, the SVD circuit must be on for at least 500 µsec. So, to obtain the SVD detection result, follow the programming sequence below. Set SVDON to "1" Maintain for 500 µsec minimum Set SVDON to "0"...

  • Page 187: Precautions On Mounting

    SIC63616-(Rev. 1.0) NO. P179 5.3 Precautions on Mounting <Oscillation Circuit> ● Oscillation characteristics change depending on conditions (board pattern, components used, etc.). In particular, when a ceramic oscillator or crystal oscillator is used, use the oscillator manufacturer's recommended values for constants such as capacitance and resistance. ●...

  • Page 188: Chapter 7 E Lectrical C Haracteristics

    SIC63616-(Rev. 1.0) NO. P180 <Arrangement of Signal Lines> ● In order to prevent generation of electromagnetic induction noise caused by mutual inductance, do not arrange a large current signal line near the circuits that are sensitive to noise such as the oscillation unit and analog input unit.

  • Page 189: Lcd Panel

    40 × 32, 48 × 24, or 56 × 16 P10–P13 P20–P23 P40–P43 RESET Cres 5.5 V RFOUT/P03 1.6 V SEN0/P02 S1C63616 REF0/P01 REF1 RFIN0/P00 [The potential of the substrate (back of the chip) is V SEN1 REF1 REF2 RFIN1...

  • Page 190: Absolute Maximum Rating

    SIC63616-(Rev. 1.0) NO. P182 chapter lectrical haracteriSticS 7.1 Absolute Maximum Rating =0V) Item Symbol Condition Rated value Unit Power supply voltage -0.3 to +6.0 LCD power supply voltage -0.3 to +6.0 Input voltage -0.3 to V + 0.3 Output voltage -0.3 to V + 0.3 High level output current...

  • Page 191: Dc Characteristics

    SIC63616-(Rev. 1.0) NO. P183 7.3 DC Characteristics Unless otherwise specified: =1.6 to 5.5V, V =0V, Ta=-45 to 85°C Item Symbol Condition Min. Typ. Max. Unit P1x, P2x, P4x ∗1 High level input voltage 0.8V – P1x, P2x, P4x ∗1 Low level input voltage –...

  • Page 192: Analog Circuit Characteristics And Current Consumption

    SIC63616-(Rev. 1.0) NO. P184 7.4 Analog Circuit Characteristics and Current Consumption LCD drive voltage (1/5 bias, V reference) Unless otherwise specified: =1.6 to 5.5V, V =0V, Ta=25°C, C =0.1µF, When a checker pattern is displayed, No panel load 2– A 1 MΩ load resistor is connected between V –V –V –V...
  • Page 193 SIC63616-(Rev. 1.0) NO. P185 LCD drive voltage (1/4 bias, V reference) Unless otherwise specified: =1.6 to 5.5V, V =0V, Ta=25°C, C =0.1µF, When a checker pattern is displayed, No panel load 2– A 1 MΩ load resistor is connected between V –V –V –V...

  • Page 194: Current Consumption

    SIC63616-(Rev. 1.0) NO. P186 Current consumption Unless otherwise specified: =1.6 to 5.5V, V =0V, DBON=HLON=0(V =OFF), FLCKSx=0H(32Hz), Ta=25°C, No panel load Item Symbol Condition Min. Typ. Max. Unit Current consumption in SLEEP When SLP is executed: OSC1=ON, OSC3=OFF – 0.08 0.50 µA Current consumption in HALT...

  • Page 195: Oscillation Characteristics

    SIC63616-(Rev. 1.0) NO. P187 7.5 Oscillation Characteristics The oscillation characteristics change depending on the conditions (components used, board pattern, etc.). Use the following characteristics as reference values. OSC1 crystal oscillation circuit Unless otherwise specified: =1.6 to 5.5V, V =0V, Crystal oscillator=C-002RX(R =30kΩ(Typ.), C =12.5pF), Ta=25°C Item...

  • Page 196: Serial Interface Ac Characteristics

    SIC63616-(Rev. 1.0) NO. P188 7.6 Serial Interface AC Characteristics Master mode Condition: V =3.0V, V =0V, Ta=-45 to 85°C, V =0.8V =0.2V =0.8V =0.2V Item Symbol Min. Typ. Max. Unit Transmitting data output delay time – – Receiving data input set-up time –...
  • Page 197 SIC63616-(Rev. 1.0) NO. P189 7.7 Timing Chart System clock switching OSCC 10 msec min. ∗ CLKCHG ∗ 1 instruction execution time or longer 3240-0412...
  • Page 198 SIC63616-(Rev. 1.0) NO. P190 7.8 Characteristics Curves (reference value) High level output current-voltage characteristic Ta = 85°C, Max. value –V = 1.6 V = 3.0 V = 5.5 V Low level output current-voltage characteristic Ta = 85°C, Min. value = 5.5 V = 3.0 V = 1.6 V 3240-0412...
  • Page 199 SIC63616-(Rev. 1.0) NO. P191 LCD drive voltage - supply voltage characteristic (1/5 bias, V reference, power supply voltage booster/halver not used) Ta = 25°C, Typ. value LCx = FH LCx = 0H LCD drive voltage - supply voltage characteristic (1/5 bias, V reference, power supply voltage booster/halver used) Ta = 25°C, Typ.
  • Page 200 SIC63616-(Rev. 1.0) NO. P192 LCD drive voltage - supply voltage characteristic (1/4 bias, V reference, power supply voltage booster/halver not used) Ta = 25°C, Typ. value LCx = FH LCx = 0H LCD drive voltage - supply voltage characteristic (1/4 bias, V reference, power supply voltage booster/halver used) Ta = 25°C, Typ.
  • Page 201 SIC63616-(Rev. 1.0) NO. P193 LCD drive voltage - ambient temperature characteristic (1/5 bias, V reference, power supply voltage booster/halver not used) = 3.0 V, Typ. value 1.05V 1.04V 1.03V 1.02V 1.01V 1.00V 0.99V 0.98V 0.97V 0.96V 0.95V 0.94V Ta [°C] LCD drive voltage - ambient temperature characteristic (1/4 bias, V reference, power supply voltage booster/halver not used)
  • Page 202 SIC63616-(Rev. 1.0) NO. P194 LCD drive voltage - load characteristic (1/5 bias, V reference, power supply voltage booster/halver not used) When a load is connected to V terminal only LCx = FH, Ta = 25°C, Typ. value 5.80 5.75 5.70 5.65 5.60 5.55...
  • Page 203 SIC63616-(Rev. 1.0) NO. P195 SVD voltage - ambient temperature characteristic SVDSx = FH, Typ. value 1.05V 1.04V 1.03V 1.02V 1.01V 1.00V 0.99V 0.98V 0.97V 0.96V 0.95V Ta [°C] 3240-0412...
  • Page 204 SIC63616-(Rev. 1.0) NO. P196 HALT state current consumption - temperature characteristic (During operation with OSC1) <Crystal oscillation, f = 32.768 kHz> OSC1 = 5.5 V, OSC3 = OFF, Clock manager = OFF, Typ. value Ta [°C] RUN state current consumption - temperature characteristic (During operation with OSC1) <Crystal oscillation, f = 32.768 kHz>...
  • Page 205 SIC63616-(Rev. 1.0) NO. P197 RUN state current consumption - frequency characteristic (During operation with OSC3) <Ceramic oscillation> = 5.5 V, Ta = 25°C, Typ. value OSC3 frequency [MHz] RUN state current consumption - resistor characteristic (During operation with OSC3) <CR oscillation> = 5.5 V, Ta = 25°C, Typ.
  • Page 206 SIC63616-(Rev. 1.0) NO. P198 Oscillation frequency - resistor characteristic (OSC3) <CR oscillation> = 5.5 V, Ta = 25°C, Typ. value 10000 1000 1000 [kΩ] Oscillation frequency - temperature characteristic (OSC3) <CR oscillation> = 30 kΩ, Typ. value 10000 1000 Ta [°C] 3240-0412...
  • Page 207 SIC63616-(Rev. 1.0) NO. P199 RFC reference/sensor oscillation frequency - resistance characteristic (DC oscillation mode) = 1000 pF, Ta = 25°C, Typ. value 10,000 1,000 IC deviation = 1.6 V = 5.5 V 1,000 10,000 [kΩ] RFC reference/sensor oscillation frequency - resistance characteristic (AC oscillation mode) = 1000 pF, Ta = 25°C, Typ.
  • Page 208 SIC63616-(Rev. 1.0) NO. P200 RFC reference/sensor oscillation frequency - capacitance characteristic (DC/AC oscillation mode) = 100 kΩ, Ta = 25°C, Typ. value 1,000 IC deviation = 1.6 V = 5.5 V 1,000 10,000 [pF] RFC reference/sensor oscillation frequency - current consumption characteristic (DC/AC oscillation mode) = 1000 pF, Ta = 25°C, Typ.

  • Page 209: Plastic Package

    SIC63616-(Rev. 1.0) NO. P201 Chapter aCkage 8.1 Plastic Package TQFP15-128pin (Unit: mm) INDEX 0.13min 0.23max 0.09min 0.2max 0° 10° 0.3 min 0.75 max The dimensions are subject to change without notice. 3240-0412...

  • Page 210: Ceramic Package For Test Samples

    SIC63616-(Rev. 1.0) NO. P202 8.2 Ceramic Package for Test Samples QFP17-144pin (Unit: mm) 22.00 ±0.25 19.20 ±0.19 0.50 0.20 0.50 ±0.20 3240-0412...
  • Page 211 SIC63616-(Rev. 1.0) NO. P203 Chapter ayout 9.1 Diagram of Pad Layout (0, 0) Die No. 3.124mm Chip thickness: 400 µm 77 × 85 µm Pad opening: 3240-0412...

  • Page 212: Pad Coordinates

    SIC63616-(Rev. 1.0) NO. P204 9.2 Pad Coordinates Unit: mm Pad name Pad name Pad name SEG18 -1.130 -1.532 1.471 -0.145 RFIN1 -0.840 1.532 SEG19 -1.040 -1.532 1.471 -0.055 REF1 -0.930 1.532 SEG20 -0.950 -1.532 1.471 0.035 SEN1 -1.020 1.532 SEG21 -0.860 -1.532 1.471...
  • Page 213 Note: For the software development of S1C63616, use the Peripheral Circuit Board for S1C6F632. For the S1C63 Family Peripheral Circuit Board (S5U1C63000P6), download the circuit data for S1C6F632. This section describes how to use the Peripheral Circuit Boards for the S1C6F632 (S5U1C63000P6 and S5U1C6F632P2), which provide emulation functions when mounted on the debugging tool for the S1C63 Family of 4-bit single-chip microcomputers, the ICE (S5U1C63000H2/S5U1C63000H6).
  • Page 214 SIC63616-(Rev. 1.0) NO. P206 (4) Register monitor pins These pins correspond one-to-one to the registers and motor driver outputs listed below. The pin out- puts a high for logic "1" and a low for logic "0". Monitor Pin No. Name LED No.
  • Page 215 SIC63616-(Rev. 1.0) NO. P207 (7) RESET switch This switch initializes the internal circuits of this board and feeds a reset signal to the ICE. (8) External part connecting socket Unused (9) CLK and PRG switch If power to the ICE is shut down before circuit data downloading is complete, the circuit configuration in this board will remain incomplete, and the debugger may not be able to start when you power on the ICE once again.
  • Page 216 The S5U1C6F632P2 board provides the R/f converter function that supports resistive sensors such as a thermistor and resistive humidity sensors and the LCD driver function. The following explains the names and functions of each part of the S5U1C6F632P2 board. S1C63632 ADD ON BOARD SEIKO EPSON CORP. RFOUT SEN1 SEN0...
  • Page 217 SIC63616-(Rev. 1.0) NO. P209 (3) CN3 (P0 I/O connector) This is a user connector to input/output the P00 to P03 port signals. The P00 to P03 terminals of the actual IC are shared with the terminals for R/f converter channel 0. The S5U1C6F632P2 board provides this connector separated with the R/f converter socket and monitor pins shown in (1) above.
  • Page 218 SIC63616-(Rev. 1.0) NO. P210 A.2 Connecting to the Target System This section explains how to connect the target system. First insert the S5U1C63000P6 board into the second upper slot of the ICE and the S5U1C6F632P2 board into the top slot. Download the circuit data to the S5U1C63000P6 board before installing the S5U1C6F632P2 board if the S5U1C63000P6 board does not include the correct circuit data.
  • Page 219 To connect the S5U1C63000P6 and S5U1C6F632P2 to the target system, use the I/O connecting cables supplied with these boards. Take care when handling the connectors, since they conduct electrical power = +3.3 V). 1/5 bias 1/4 bias DIAG S5U1C63000H6 EPSON S5U1C6F632P2 CN4 S5U1C63000P6 CN1 S5U1C6F632P2 CN3 (80 pins) (80 pins)
  • Page 220 SIC63616-(Rev. 1.0) NO. P212 Table A.2.1 S5U1C63000P6 I/O connector pin assignment 40-pin CN1-1 connector 40-pin CN1-2 connector Pin name Pin name (= 3.3 V) (= 3.3 V) (= 3.3 V) (= 3.3 V) Cannot be connected Cannot be connected Cannot be connected Cannot be connected Cannot be connected Cannot be connected...
  • Page 221 SIC63616-(Rev. 1.0) NO. P213 Table A.2.2 S5U1C6F632P2 I/O connector pin assignment 10-pin CN3 connector 40-pin CN4-1 connector 40-pin CN4-2 connector Pin name Pin name Pin name (= 3.3 V) COM0 SEG24 (= 3.3 ) COM1 SEG25 COM2 SEG26 COM3 SEG27 COM4 SEG28 COM5...
  • Page 222 SIC63616-(Rev. 1.0) NO. P214 A.3 Downloading to S5U1C63000P6 Note: The S1C6F632 circuit data is available only for the S5U1C63000P6, and it cannot be downloaded to the previous S5U1C63000P1 board. A.3.1 Downloading Circuit Data 1 - when new ICE (S5U1C63000H2/S5U1C63000H6) is used The S5U1C63000P6 board comes with the FPGA that contains factory inspection data, therefore the circuit data for the model to be used should be downloaded.
  • Page 223 SIC63616-(Rev. 1.0) NO. P215 A.3.2 Downloading Circuit Data 2 - when previous ICE (S5U1C63000H1) is used The standard ICE (S5U1C63000H1, previous model) did not support the circuit data download function for the S5U1C63000P6 board. To use the download function, update the ICE firmware according to the follow- ing procedure.
  • Page 224 SIC63616-(Rev. 1.0) NO. P216 A.4 Usage Precautions To ensure correct use of the peripheral circuit board, please observe the following precautions. A.4.1 Operational precautions (1) Before inserting or removing cables, turn off power to all pieces of connected equipment. (2) Do not turn on power or load mask option data if all of the I/O ports (P10–P13) are held low. Doing so may activate the multiple key entry reset function.
  • Page 225 OSC3 oscillation circuit by mask option. <Access to undefined address space> If any undefined space in the S1C63616's internal ROM/RAM or I/O is accessed for data read or write operations, the read/written value is indeterminate. Additionally, it is important to remain aware that indeterminate state differs between S5U1C63000P6 and the actual IC.
  • Page 226 SIC63616-(Rev. 1.0) NO. P218 <I/O ports> - Do not set the P1x ports used for multiple key entry reset to output mode as the S5U1C63000P6 and S5U1C6F632P2 may be reset. - Do not enable the input interrupt or peripheral input function of the I/O port that has been set to out- put mode.
  • Page 227 SIC63616-(Rev. 1.0) NO. P219 A.5 Product Specifications A.5.1 Specifications of S5U1C63000P6 S5U1C63000P6 Dimension: 254 mm (wide) × 144.8 mm (depth) × 16 mm (height) (including screws) Weight: Approx. 250 g Power supply: DC 5 V ± 5%, less than 1 A (supplied from ICE main unit) I/O connection cable (80-pin) S5U1C63000P6 connector:...
  • Page 228 SIC63616-(Rev. 1.0) NO. P220 A.5.2 Specifications of S5U1C6F632P2 S5U1C6F632P2 Dimension: 254 mm (width) × 144.8 mm (depth) × 13 mm (height) (including screws) Weight: Approx. 170 g Power supply: DC 5 V ± 5%, less than 50 mA (supplied from ICE main unit and converted into 3.3 V by the onboard regulator) I/O connection cable (80-pin) S5U1C6F632P2 connector:...

  • Page 229: Revision History

    Revision History Revision History Attachment-1 Rev. No. Date Page Category Contents Rev. 1.0 2011/03/09 First edition...
  • Page 230 EPSON HONG KONG LTD. Unit 715-723, 7/F Trade Square, 681 Cheung Sha Wan Road, Kowloon, Hong Kong. Phone: +852-2585-4600 FAX: +852-2827-4346 EPSON TAIWAN TECHNOLOGY & TRADING LTD. 14F, No. 7, Song Ren Road, Taipei 110, TAIWAN Phone: +886-2-8786-6688 FAX: +886-2-8786-6660 EPSON SINGAPORE PTE., LTD.

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