Data Transmit/Receive Control - Epson S1C17704 Technical Manual

19.5 Data Transmit/Receive Control

Before starting data transfer, set up the conditions as shown below.
(1) Set up the 16-bit timer Ch.1 to output the SPI clock. See Chapter 11.
(2) Select either master or slave mode. See Section 19.4.
(3) Set up the clock conditions. See Section 19.4.
(4) Set up the interrupt conditions if the SPI interrupt is used. See Section 19.6.
Note: Make sure that the SPI module is disabled (SPEN/SPI_CTL register = 0) before setting the
conditions above.
∗ SPEN: SPI Enable Bit in the SPI Control (SPI_CTL) Register (D0/0x4326)
Enabling data transmission/reception
First, set the SPEN bit (D0/SPI_CTL register) to 1 to enable SPI operation. This puts the SPI in ready-to-
transmit/receive status and enables clock input/output.
Note: Do not set the SPEN bit to 0 while the SPI module is transmitting/receiving data.
Data transmit control
To start transmission, write transmit data to the SPI_TXD register (0x4322).
∗ SPI_TXD: SPI Transmit Data Register (0x4322)
Data is written to the transmit data buffer and the SPI starts data transmission.
The buffered data is sent to the shift register for transmission. In master mode, the SPI module starts outputting
the clock from the SPICLK pin. In slave mode, the SPI module waits for clock input from the SPICLK pin.
The data bits in the shift register are shifted one by one at the rising or falling edge of the clock configured with
CPHA (D3/SPI_CTL register) and CPOL (D2/SPI_CTL register) (see Figure 19.4.1), and are output from the
SDO pin. The MSB of data is transmitted first.
∗ CPHA: Clock Phase Select Bit in the SPI Control (SPI_CTL) Register (D3/0x4326)
∗ CPOL: Clock Polarity Select Bit in the SPI Control (SPI_CTL) Register (D2/0x4326)
The SPI module provides two status flags for data transmit control, SPTBE (D0/SPI_ST register) and SPBSY
(D2/SPI_ST register).
∗ SPTBE: Transmit Data Buffer Empty Flag in the SPI Status (SPI_ST) Register (D0/0x4320)
∗ SPBSY: Transfer Busy Flag in the SPI Status (SPI_ST) Register (D2/0x4320)
The SPTBE flag indicates the transmit data buffer status; it goes 0 when the application program writes data to
the SPI_TXD register (transmit data buffer) and returns to 1 when the data in the transmit data buffer is sent to
the shift register for transmitting. An interrupt can be generated when this flag goes 1 (see Section 19.6). Use
this interrupt or read the SPTBE flag to check that the transmit data buffer becomes empty when transmitting
the next data. Although the transmit data buffer size is one byte, transmit data can be written while the previous
data is being transmitted as the shift register is separately provided. However, make sure that the transmit data
buffer is empty before writing transmit data. If data is written when the SPTBE flag is 0, the previous transmit
data in the transmit data buffer is overwritten with the new data.
In master mode, the SPBSY flag indicates the shift register status; it goes 1 when transmit data is loaded from
the transmit data buffer and returns to 0 upon completion of data transmission. Read this flag to check whether
the SPI module is busy or idle.
In slave mode, the SPBSY flag indicates the SPI slave select signal (#SPISS pin) status; it goes 1 when this SPI
module is selected as a slave or goes 0 when this SPI module is deselected.
S1C17704 TECHNICAL MANUAL
EPSON
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