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APPENDIX A LIST OF I/O REGISTERS
0x5200–0x5214
Register name Address
Bit
P0 Port Input
0x5200
D7–0 P0IN[7:0]
Data Register
(8 bits)
(P0_IN)
P0 Port Output
0x5201
D7–0 P0OUT[7:0] P0[7:0] port output data
Data Register
(8 bits)
(P0_OUT)
P0 Port
0x5202
D7–0 P0IO[7:0]
I/O Direction
(8 bits)
Control Register
(P0_IO)
P0 Port Pull-up
0x5203
D7–0 P0PU[7:0]
Control Register
(8 bits)
(P0_PU)
P0 Port Schmitt
0x5204
D7–0 P0SM[7:0]
Trigger Control
(8 bits)
Register
(P0_SM)
P0 Port
0x5205
D7–0 P0IE[7:0]
Interrupt Mask
(8 bits)
Register
(P0_IMSK)
P0 Port
0x5206
D7–0 P0EDGE[7:0] P0[7:0] port interrupt edge select
Interrupt Edge
(8 bits)
Select Register
(P0_EDGE)
P0 Port
0x5207
D7–0 P0IF[7:0]
Interrupt Flag
(8 bits)
Register
(P0_IFLG)
P0 Port
0x5208
D7
Chattering
(8 bits)
D6–4 P0CF2[2:0] P0[7:4] chattering filter time
Filter Control
Register
(P0_CHAT)
D3
D2–0 P0CF1[2:0] P0[3:0] chattering filter time
P0 Port Key-
0x5209
D7–2 –
Entry Reset
(8 bits)
D1–0 P0KRST[1:0] P0 port key-entry reset
Configuration
Register
(P0_KRST)
P1 Port Input
0x5210
D7–0 P1IN[7:0]
Data Register
(8 bits)
(P1_IN)
P1 Port Output
0x5211
D7–0 P1OUT[7:0] P1[7:0] port output data
Data Register
(8 bits)
(P1_OUT)
P1 Port
0x5212
D7–0 P1IO[7:0]
I/O Direction
(8 bits)
Control Register
(P1_IO)
P1 Port Pull-up
0x5213
D7–0 P1PU[7:0]
Control Register
(8 bits)
(P1_PU)
P1 Port Schmitt
0x5214
D7–0 P1SM[7:0]
Trigger Control
(8 bits)
Register
(P1_SM)
AP-22
Name
Function
P0[7:0] port input data
P0[7:0] port I/O direction select
P0[7:0] port pull-up enable
P0[7:0] port Schmitt trigger input
enable
P0[7:0] port interrupt enable
P0[7:0] port interrupt flag
–
reserved
–
reserved
reserved
configuration
P1[7:0] port input data
P1[7:0] port I/O direction select
P1[7:0] port pull-up enable
P1[7:0] port Schmitt trigger input
enable
Setting
1 1 (H)
0 0 (L)
1 1 (H)
0 0 (L)
1 Output
0 Input
1 Enable
0 Disable
1 Enable
0 Disable
(Schmitt)
1 Enable
0 Disable
1 Falling edge 0 Rising edge
1 Cause of
0 Cause of
interrupt
occurred
–
P0CF2[2:0]
0x7
16384/f
0x6
0x5
0x4
0x3
0x2
0x1
0x0
–
P0CF1[2:0]
0x7
16384/f
0x6
0x5
0x4
0x3
0x2
0x1
0x0
–
P0KRST[1:0]
Configuration
0x3
P0[3:0] = 0
0x2
P0[2:0] = 0
0x1
P0[1:0] = 0
0x0
1 1 (H)
0 0 (L)
1 1 (H)
0 0 (L)
1 Output
0 Input
1 Enable
0 Disable
1 Enable
0 Disable
(Schmitt)
EPSON
P Port & Port MUX
Init. R/W
Remarks
×
R
0
R/W
0
R/W
1
R/W
(0xff)
1
R/W
(CMOS)
(0xff)
0
R/W
0
R/W
0
R/W Reset by writing 1.
interrupt not
occurred
–
–
0 when being read.
Filter time
0
R/W
0x0 R/W
PCLK
8192/f
PCLK
4096/f
PCLK
2048/f
PCLK
1024/f
PCLK
512/f
PCLK
256/f
PCLK
None
–
–
0 when being read.
Filter time
0x0 R/W
PCLK
8192/f
PCLK
4096/f
PCLK
2048/f
PCLK
1024/f
PCLK
512/f
PCLK
256/f
PCLK
None
–
–
0 when being read.
0x0 R/W
Disable
×
R
0
R/W
0
R/W
1
R/W
(0xff)
1
R/W
(CMOS)
(0xff)
S1C17704 TECHNICAL MANUAL
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