Remc Interrupt - Epson S1C17704 Technical Manual

21 REMOTE CONTROLLER (REMC)

21.6 REMC Interrupt

The REMC module can generate the following three types of interrupts:
• Underflow interrupt
• Rising edge interrupt
• Falling edge interrupt
The REMC module has one interrupt signal to be output to the interrupt controller (ITC) and it is shared with the
three causes of interrupt. To determine the cause of interrupt that has occurred, read the interrupt flags in the REMC
module.
Underflow interrupt
This interrupt request occurs when the data length counter reaches 0 during count-down, and it sets the interrupt
flag REMUIF (D0/REMC_IFLG register) in the REMC module to 1.
During data transmission, this interrupt notifies the application program that a data transmission with the data
length specified has completed. During data reception, this interrupt notifies the application program that a data
reception has completed or a receive error has occurred.
∗ REMUIF: Underflow Interrupt Flag in the REMC Interrupt Flag (REMC_IFLG) Register (D0/0x5347)
Set the REMUIE bit (D0/REMC_IMSK register) to 1 when using this interrupt. If REMUIE is set to 0 (default),
REMUIF will not be set to 1 and an interrupt request by this cause will not be sent to the ITC.
∗ REMUIE: Underflow Interrupt Enable Bit in the REMC Interrupt Mask (REMC_IMSK) Register (D0/0x5346)
If REMUIF is set to 1, the REMC module outputs the interrupt request signal to the ITC. The interrupt request
signal sets the REMC interrupt flag in the ITC to 1 and an interrupt occurs if other interrupt conditions meet the
ITC and S1C17 Core settings.
The REMC interrupt handler routine should read the REMUIF flag to check if the interrupt has occurred due to
a data length counter underflow or another cause.
Furthermore, the interrupt handler routine must reset (write 1 to) REMUIF in the REMC module as well as the
REMC interrupt flag in the ITC, to clear the cause of interrupt.
Rising edge interrupt
This interrupt request occurs when the signal input to the REMI pin goes high from low status, and it sets the
interrupt flag REMRIF (D1/REMC_IFLG register) in the REMC module to 1.
During data reception, run the data length counter between this interrupt and the corresponding falling edge
interrupt. The receive data pulse width can be calculated from the count value.
∗ REMRIF: Rising Edge Interrupt Flag in the REMC Interrupt Flag (REMC_IFLG) Register (D1/0x5347)
Set the REMRIE bit (D1/REMC_IMSK register) to 1 when using this interrupt. If REMRIE is set to 0 (default),
REMRIF will not be set to 1 and an interrupt request by this cause will not be sent to the ITC.
∗ REMRIE: Rising Edge Interrupt Enable Bit in the REMC Interrupt Mask (REMC_IMSK) Register (D1/0x5346)
If REMRIF is set to 1, the REMC module outputs the interrupt request signal to the ITC. The interrupt request
signal sets the REMC interrupt flag in the ITC to 1 and an interrupt occurs if other interrupt conditions meet the
ITC and S1C17 Core settings.
The REMC interrupt handler routine should read the REMRIF flag to check if the interrupt has occurred due to
detection of a rising edge of the input signal or another cause.
Furthermore, the interrupt handler routine must reset (write 1 to) REMRIF in the REMC module as well as the
REMC interrupt flag in the ITC, to clear the cause of interrupt.
21-8
EPSON
S1C17704 TECHNICAL MANUAL