Uart Interrupt - Epson S1C17704 Technical Manual

18.7 UART Interrupt

The UART can generate the following three types of interrupts:
• Transmit buffer empty interrupt
• Receive buffer full interrupt
• Receive error interrupt
The UART has one interrupt signal to be output to the interrupt controller (ITC) and it is shared with all three
causes of interrupt. To determine the cause of interrupt that has occurred, read the status and error flags.
Transmit buffer empty interrupt
Set the TIEN bit (D4/UART_CTL register) to 1 when using this interrupt. If TIEN is set to 0 (default), an
interrupt request by this cause will not be sent to the ITC.
∗ TIEN: Transmit Buffer Empty Interrupt Enable Bit in the UART Control (UART_CTL) Register (D4/0x4104)
When the transmit data set in the transmit data buffer is transferred to the shift register, the UART sets the
TDBE bit (D0/UART_ST register) to 1 to indicate that the transmit data buffer is empty. At the same time, the
UART outputs an interrupt request pulse to the ITC if the transmit buffer empty interrupt has been enabled (TIEN
= 1).
∗ TDBE: Transmit Data Buffer Empty Flag in the UART Status (UART_ST) Register (D0/0x4100)
If other interrupt conditions are satisfied, an interrupt is generated.
The UART interrupt handler routine should read the TDBE flag to check if the interrupt has occurred due to a
transmit buffer empty or another cause. When TDBE = 1, the UART interrupt handler routine can write the next
transmit data to the transmit data buffer.
Receive buffer full interrupt
Set the RIEN bit (D5/UART_CTL register) to 1 when using this interrupt. If RIEN is set to 0 (default), an
interrupt request by this cause will not be sent to the ITC.
∗ RIEN: Receive Buffer Full Interrupt Enable Bit in the UART Control (UART_CTL) Register (D5/0x4104)
When the specified number of received data is loaded to the receive data buffer, the UART outputs an interrupt
request pulse to the ITC if the receive buffer full interrupt has been enabled (RIEN = 1). If the RBFI bit (D1/
UART_CTL register) is 0, an interrupt request pulse is output when received data is loaded to the receive data
buffer (when the RDRY flag (D1/UART_ST register) goes 1). If the RBFI bit (D1/UART_CTL register) is 1,
an interrupt request pulse is output when two received data occupy the receive data buffer (when the RD2B flag
(D3/UART_ST register) goes 1).
∗ RBFI: Receive Buffer Full Interrupt Condition Setup Bit in the UART Control (UART_CTL) Register (D1/0x4104)
∗ RDRY: Receive Data Ready Flag in the UART Status (UART_ST) Register (D1/0x4100)
∗ RD2B: Second Byte Receive Flag in the UART Status (UART_ST) Register (D3/0x4100)
If other interrupt conditions are satisfied, an interrupt is generated.
The UART interrupt handler routine should read the RDRY and RD2B flags to check if the interrupt has
occurred due to a receive buffer full or another cause. When RDRY or RD2B = 1, the UART interrupt handler
routine can read the received data from the receive data buffer.
S1C17704 TECHNICAL MANUAL
EPSON
18 UART
18-9