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0x50a6: LCD Interrupt Flag Register (LCD_IFLG)
Register name Address
Bit
LCD Interrupt
0x50a6
D7–1 –
Flag Register
(8 bits)
(LCD_IFLG)
D0
D[7:1]
Reserved
D0
FRMIF: Frame Signal Interrupt Flag
This is the interrupt flag to indicate the frame interrupt cause occurrence status.
1 (R):
Cause of interrupt has occurred
0 (R):
No cause of interrupt has occurred (default)
1 (W):
Flag is reset
0 (W):
Has no effect
FRMIF is the interrupt flag for the LCD module. The interrupt flag is set to 1 at the rising edge of the
frame signal. If FRMIE (D0/LCD_IMSK register) has been set to 1 at this time, the LCD interrupt
request signal is output to the ITC. The interrupt request signal sets the LCD interrupt flag in the ITC to
1 and an interrupt occurs if other interrupt conditions meet the ITC and S1C17 Core settings.
The settings shown below are required to manage the cause-of-interrupt occurrence status using this
register.
1. Set the LCD interrupt trigger mode in the ITC to level trigger.
2. After an interrupt occurs, reset the LCD interrupt flag of the LCD module in the interrupt handler
routine (this also resets the interrupt flag in the ITC).
The FRMIF flag is reset by writing 1.
Note: To avoid occurrence of unnecessary interrupts, be sure to reset the FRMIF flag before the
LCD interrupt is enabled using FRMIE.
S1C17704 TECHNICAL MANUAL
Name
Function
reserved
FRMIF
Frame signal interrupt flag
EPSON
Setting
Init. R/W
–
1 Occurred
0 Not occurred
22 LCD DRIVER (LCD)
Remarks
–
–
0 when being read.
0
R/W Reset by writing 1.
22-21
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