Setting Compare Data - Epson S1C17704 Technical Manual

13 PWM & CAPTURE TIMER (T16E)

13.4 Setting Compare Data

Selecting compare data register/buffer
The PWM & capture timer contains two data comparators that allows the count data to be compared with given
values. The compare data A and B registers are used to set these values. These registers can be directly read and
written.
Furthermore, compare data can be set via the compare data buffer. In this case, the set value is loaded to the
compare data register when the counter is reset by the compare B match signal or software (by writing 1 to
T16ERST).
Select whether compare data is written to the compare data register or the buffer using CBUFEN (D5/0x5306).
∗ CBUFEN: Comparison Buffer Enable Bit in the PWM Timer Control (T16E_CTL) Register (D5/0x5306)
When 1 is written to CBUFEN, the compare data buffer is selected; when 0 is written, the compare data register
is selected.
At initial reset, the compare data register is selected.
Writing compare data
Write compare data A to T16ECA[15:0] (D[15:0]/T16E_CA register) and compare data B to T16ECB[15:0]
(D[15:0]/T16E_CB register).
∗ T16ECA[15:0]: Compare Data A in the PWM Timer Compare Data A (T16E_CA) Register (D[15:0]/0x5300)
∗ T16ECB[15:0]: Compare Data B in the PWM Timer Compare Data B (T16E_CB) Register (D[15:0]/0x5302)
When CBUFEN is set to 0, these registers allow direct reading/writing from/to the compare data register.
When CBUFEN is set to 1, these registers are used to read/write from/to the compare data buffer. The content
of the buffer is loaded to the compare data register when the counter is reset.
At initial reset, the compare data registers/buffers are set to 0x0.
The timer compares the compare data register and count data and, when the two values are equal, generates a
compare match signal. This compare match signal controls the clock output (TOUT signal) to external devices,
in addition to generating an interrupt.
The compare data B is also used to reset the counter.
The counter reset period is calculated by the expression below.
Counter reset period = ———— [s]
Counter reset cycle = ———— [Hz]
CB: Compare data B (T16E_CB register value)
clk_in: Prescaler output clock frequency
13-4
CB + 1
clk_in
clk_in
CB + 1
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S1C17704 TECHNICAL MANUAL