Epson S1C17704 Technical Manual page 421

Cmos 16-bit single chip microcomputer
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; ----- ITC (interrupt controller) ------
Xld.a
%r7, 0x4300
Xld.a
%r0, 0x1010
ext
0x06
ld
[%r7], %r0
Xld.a
%r0, 0x1010
ext
0x08
ld
[%r7], %r0
Xld.a
%r0, 0x1010
ext
0x0a
ld
[%r7], %r0
Xld.a
%r0, 0x1010
ext
0x0c
ld
[%r7], %r0
; ===== Main routine =========================================
...
; ======================================================================
;
Interrupt handler
; ======================================================================
; ----- Address unalign --------------------------
unalign_handler:
...
; ----- NMI -------------------------------------
nmi_handler:
...
(1) Declare a .rodata section to locate the vector table in the .vector section.
(2) Define addresses of the interrupt handler routines as vectors.
The intXX_handler symbols can be used for software interrupts.
(3) Describe the program code in a .text section.
(4) Set the stack pointer.
(5) Set the number of access cycles for the Flash controller.
One-cycle access can be specified only when the system clock frequency is 6 MHz or lower.
(See Chapter 3, "Memory Map, Bus Control.")
(6) Set the number of access cycles for the SRAM controller.
(See Chapter 3, "Memory Map, Bus Control.")
(7) Set the interrupt trigger mode for the peripheral modules listed below to level trigger.
P0 port, P1 port, stopwatch timer, clock timer, 8-bit OSC1 timer, SVD, LCD driver, PWM & capture timer
(See Chapter 6, "Interrupt Controller (ITC).")
S1C17704 TECHNICAL MANUAL
; ITC register base address
; P0, P1 interrupt level & trigger mode
; [0x4306] <= 0x1010
; SWT, CT interrupt level & trigger mode
; [0x4308] <= 0x1010
; T8OSC1, SVD interrupt level & trigger mode
; [0x430a] <= 0x1010
; LCD, T16E interrupt level & trigger mode
; [0x430c] <= 0x1010
EPSON
APPENDIX E INITIALIZE ROUTINE
...(7)
...(7)
...(7)
...(7)
AP-39

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