Interrupt Processing By The S1C17 Core - Epson S1C17704 Technical Manual

Cmos 16-bit single chip microcomputer
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6 INTERRUPT CONTROLLER (ITC)

6.3.6 Interrupt Processing by the S1C17 Core

A maskable interrupt to the S1C17 Core occurs when all of the conditions described below are met.
• The ITEN bit (D0/ITC_CTL register) is set to 1.
∗ ITEN: ITC Enable Bit in the ITC Control (ITC_CTL) Register (D0/0x4304)
• The interrupt enable bit for the cause of interrupt that has occurred is set to 1.
• The IE (Interrupt Enable) bit of the PSR (Processor Status Register) in the S1C17 Core is set to 1.
• The cause of interrupt that has occurred has a higher interrupt level than the value that is set in the IL field of the
PSR.
• No other cause of interrupt having higher priority, such as NMI, has occurred.
When a cause of interrupt occurs, the corresponding interrupt flag is set to 1 and the flag remains set until it is reset
in the software program or by the hardware for a level triggered interrupt. Therefore, in no cases can the generated
cause of interrupt be inadvertently cleared even if the above conditions are not met when the cause of interrupt has
occurred. The interrupt will occur when the above conditions are met.
If two or more maskable causes of interrupt occur simultaneously, the cause of interrupt that has the highest priority
is allowed to signal an interrupt request to the S1C17 Core. The other interrupts with lower priorities are kept
pending until the above conditions are met.
The S1C17 Core keeps sampling interrupt requests every cycle. When the S1C17 Core accepts an interrupt request,
it enters interrupt processing after completing execution of the instruction that was being executed.
The following lists the contents executed in interrupt processing.
(1) The PSR and the current program counter (PC) value are saved to the stack.
(2) The IE bit of the PSR is reset to 0 (following maskable interrupts are disabled).
(3) The IL of the PSR is set to the interrupt level of the accepted interrupt (NMI does not change the interrupt
level).
(4) The vector of the interrupt occurred is loaded into the PC, thus executing the interrupt handler routine.
Thus, once an interrupt is accepted, all maskable interrupts that may follow are disabled in (2). Multiple interrupts
can also be handled by setting the IE bit to 1 in the interrupt handler routine. In this case, since the IL has been
changed in (3), only an interrupt that has a higher level than that of the currently processed interrupt is accepted.
When the interrupt handler routine is terminated by the reti instruction, the PSR is restored to its previous status
before the interrupt has occurred. The program restarts processing after branching to the instruction next to the one
that was being executed when the interrupt occurred.
6-8
EPSON
S1C17704 TECHNICAL MANUAL

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