Initial Reset; Reset Terminal (Reset); Internal Register At Initial Resetting - Epson S1C6P366 Technical Manual

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

2.2 Initial Reset

To initialize the S1C6P366 circuits, initial reset must be executed. The S1C6P366 supports an external
initial reset using the reset (RESET) terminal.
When the power is turned on, be sure to initialize using this reset function. It is not guaranteed that the
circuits are initialized by only turning the power on.
Figure 2.2.1 shows the configuration of the initial reset circuit.
OSC1
OSC2
RESET

2.2.1 Reset terminal (RESET)

Initial reset can be executed externally by setting the reset terminal to a low level (V
initial reset is released by setting the reset terminal to a high level (V
The reset input signal is maintained by the RS latch and becomes the internal initial reset signal. The RS
latch is designed to be released by a 2 Hz signal (high) that is divided by the OSC1 clock. Therefore in
normal operation, a maximum of 250 msec (when f
reset is released after the reset terminal goes to high level. Be sure to maintain a reset input of 0.1 msec or
more.
However, when turning the power on, the reset terminal should be set at a low level as in the timing
shown in Figure 2.2.1.1.
The reset terminal should be set to 0.1•V
more. After that, a level of 0.5•V
In the S1C6P366, a low level input to the reset terminal initializes some analog circuits as well as the
internal logic. At this time, 10 µA or more current is consumed as the bias current.

2.2.2 Internal register at initial resetting

Initial reset initializes the CPU as shown in Table 2.2.2.1.
The registers and flags which are not initialized by initial reset should be initialized in the program if
necessary.
In particular, the stack pointers SP1 and SP2 must be set as a pair because all the interrupts including
NMI are masked after initial reset until both the SP1 and SP2 stack pointers are set with software.
When data is written to the EXT register, the E flag is set and the following instruction will be executed in
the extended addressing mode. If an instruction which does not permit extended operation is used as the
following instruction, the operation is not guaranteed. Therefore, do not write data to the EXT register for
initialization only.
Refer to the "S1C63000 Core CPU Manual" for extended addressing and usable instructions.
8
OSC1
oscillation
circuit
V
DD
Fig. 2.2.1 Configuration of initial reset circuit
OSC1
2.7 V
V
DD
RESET
Power on
Fig. 2.2.1.1 Initial reset at power on
or less (low level) until the supply voltage becomes 2.7 V or
DD
or less should be maintained more than 2.0 msec.
DD
EPSON
2 Hz
Divider
R Q
S
) and the CPU starts operation.
DD
= 32.768 kHz) is needed until the internal initial
2.0 msec or more
0.5•V
DD
0.1•V or less (low level)
DD
Internal
initial
reset
). After that the
SS
S1C6P366 TECHNICAL MANUAL