0X5062: Noise Filter Enable Register (Osc_Nfen) - Epson S1C17704 Technical Manual

7 OSCILLATOR (OSC)

0x5062: Noise Filter Enable Register (OSC_NFEN)

Register name Address Bit
Noise Filter 0x5062 D7–2 –
Enable Register (8 bits)
D1
(OSC_NFEN)
D0
D[7:2] Reserved
D1 RSTFE: Reset Noise Filter Enable Bit
Enables/disables the noise filter for the RESET input.
1 (R/W): Enable (reject noise) (default)
0 (R/W): Disable (bypass)
When the noise filter is enabled, RESET pulses that have a width of 16 system clock (OSC1 or OSC3
clock) cycles or more will pass through the filter and are input to the S1C17 Core. Pulses that have a
width of less than 16 cycles will be rejected as noise. Enable the filter under normal circumstances.
D0 NMIFE: NMI Noise Filter Enable Bit
Enables/disables the noise filter for the NMI input.
1 (R/W): Enable (reject noise)
0 (R/W): Disable (bypass) (default)
When the noise filter is enabled, NMI pulses that have a width of 16 system clock (OSC1 or OSC3
clock) cycles or more will pass through the filter and are input to the S1C17 Core. Pulses that have a
width of less than 16 cycles will be rejected as noise.
Note: Although the S1C17704 has no external NMI input pin, the NMI request signal of the
watchdog timer passes through the filter.
7-14
Name Function
reserved
RSTFE Reset noise filter enable
NMIFE NMI noise filter enable
Setting
–
1 Enable 0 Disable
1 Enable 0 Disable
EPSON
Init. R/W Remarks
– – 0 when being read.
1 R/W
0 R/W
S1C17704 TECHNICAL MANUAL