0X5080: Pclk Control Register (Clg_Pclk) - Epson S1C17704 Technical Manual

0x5080: PCLK Control Register (CLG_PCLK)

Register name Address Bit
PCLK Control 0x5080 D7–2 –
Register (8 bits)
D1–0 PCKEN[1:0] PCLK enable
(CLG_PCLK)
D[7:2] Reserved
D[1:0] PCKEN[1:0]: PCLK Enable Bits
Enables/disables supplying the clock (PCLK) to the internal peripheral modules.
PCKEN[1:0] is set to 0x3 and the clock supply is enabled by default. When the peripheral modules
listed below are not used, disable the clock supply to reduce current consumption.
Peripheral modules that operate with PCLK
• Prescaler (PWM & capture timer, remote controller, P port)
• UART
• 8-bit timer
• 16-bit timer Ch.0–2
• Interrupt controller
• SPI
• I 2 C
• SVD circuit
• Power control circuit
• P port & port MUX
• PWM & capture timer
• MISC register
• Remote controller
The peripheral modules listed below operate with a clock other than PCLK except for accessing their
control registers. Therefore, PCLK is not required after the control registers are set once and the module
starts operating.
• Clock timer
• Stopwatch timer
• Watchdog timer
• 8-bit OSC1 timer
• LCD driver
Note: Be sure to avoid setting PCKEN[1:0] to 0x2 or 0x1, as it stops some peripheral modules.
S1C17704 TECHNICAL MANUAL
Name Function
reserved
Table 8.4.2 PCLK Control
PCKEN[1:0]
0x3
0x2
0x1
0x0
EPSON
8 CLOCK GENERATOR (CLG)
Setting
–
PCKEN[1:0] PCLK supply
0x3 Enable
0x2 Not allowed
0x1 Not allowed
0x0 Disable
PCLK supply
Enable (On)
Not allowed
Not allowed
Disable (Off)
(Default: 0x3)
Init. R/W Remarks
– – 0 when being read.
0x3 R/W
8-5