Clock Generator (Clg); Configuration Of Clock Generator - Epson S1C17704 Technical Manual

8 Clock Generator (CLG)

8.1 Configuration of Clock Generator

The clock generator controls supplying the system clock to the S1C17 Core and peripheral modules.
Figure 8.1.1 shows the structure of the clock system and the CLG module.
SLEEP, On/Off control
OSC3
OSC3
oscillator
(8.2 MHz)
OSC4
FOUT3
FOUT3
output circuit
On/Off control
SLEEP, On/Off control
OSC1
OSC1
oscillator
(32.768 kHz)
OSC2
FOUT1
FOUT1
output circuit
On/Off control
Noise filter
RESET
On/Off control
Noise filter
NMI
On/Off control
OSC3
Current consumption can be reduced by controlling the clocks according to the processing requirements as well as by
using the standby mode. For methods to reduce current consumption, see Appendix C, "Power Saving."
S1C17704 TECHNICAL MANUAL
OSC
wakeup
Clock source select
Wait circuit for OSC3
wakeup
OSC1
Divider
(1/1–1/4)
Division ratio select
S1C17 Core
S1C17 Core
Clock source select
Divider
(1/32–1/512)
OSC1
Division ratio select
Figure 8.1.1 Structure of the CLG Module
Gear select
System
clock Clock gear
(1/1–1/8)
On/Off control
Gate
On/Off control
Gate
Divider
OSC1
(1/128)
Gate
(1/1–1/32)
Division ratio select On/Off control
Gate
On/Off control
EPSON
8 CLOCK GENERATOR (CLG)
CLG
HALT
Gate CCLK S1C17 Core
Gate BCLK Internal bus, RAM,
Flash
HALT
ITC, T16, T8F,
UART, SPI, I2C,
T16E, P, MISC,
PCLK
VD1, SVD, REMC,
Control registers
(CT, SWT, WDT,
T8OSC1, LCD)
PSC
T8F, T16, T16E,
Divider
REMC, P, UART,
(1/1–1/16K)
SPI, I2C
CLK_256Hz CT, SWT, WDT
T8OSC1
SVD
LCLK LCD
8-1