Epson S1C17704 Technical Manual page 286

2
20 I C
7-bit address
10-bit address
First transmit data
Second transmit data
Figure 20.5.2 Transmit Data to Specify Slave Address and Data Direction
The transfer direction bit specifies the direction for the data transfer that follows the slave address transfer. Set
the transfer direction bit to 0 when transmitting data from the master to the slave; set it to 1 when receiving data
from the slave.
Configure an 8-bit data as above and set it into the transmit/receive data register. After that control data
transmission as described below.
The slave address with a transfer direction bit must be sent once after a START condition has been generated.
After a slave address has been sent, perform data transmission or data reception as many times as necessary. It
is necessary to perform data transmission or data reception according to the transfer direction specified with the
slave address.
Data transmit control
The following explains how to transmit data. The slave address should be sent in the same way.
To transmit byte data, set the data to the RTDT[7:0] bits (D[7:0]/I2C_DAT register). At the same time, set the
TXE bit (D9/I2C_DAT register) to 1 to execute one byte data transmission.
∗ RTDT[7:0]: Receive/Transmit Data Bits in the I
∗ TXE: Transmit Execution Bit in the I
When the TXE bit is set to 1, the I
condition is being generated or the previous data is being transferred, the I
after waiting for completion of the process.
2
First, the I C module transfer the written data to the shift register and starts outputting the clock from the SCL
pin. At this time, TXE is reset to 0 and a cause of interrupt occurs. This allows the program to set the next
transmit data and TXE again.
The data bits in the shift register are shifted one by one at the falling edge of the clock and are output from the
SDA pin. The MSB is transmitted first.
2
The I C module outputs nine clocks for one data transmission. In the ninth clock cycle, the I
SDA signal into high-impedance status to input an ACK or NACK bit from the slave.
If the slave could receive byte data, it returns an ACK (0) bit to the master. If the slave could not receive byte
data, the SDA line is not pulled down. The I
fails).
SDA (output)
SDA (input)
SCL (output)
20-6
D7 D6 D5 D4
A6 A5 A4 A3
Slave address
D7 D6 D5 D4
1 1 1 1
D7 D6 D5 D4
A7 A6 A5 A4
8 low order slave address bits
2
C Data (I2C_DAT) Register (D9/0x4344)
2
C module starts data transmission in sync with the clock. If a START
2
C module regards this status as a NACK (1) returned (transmission
D7
1
START condition
Figure 20.5.3 ACK and NACK
D3 D2 D1 D0
A2 A1 A0 DIR
Transfer direction
0: master → slave (transmission)
1: slave → master (reception)
D3 D2 D1 D0
0 A9 A8 DIR
Transfer direction
2 high order
0: master → slave (transmission)
slave address bits
1: slave → master (reception)
D3 D2 D1 D0
A3 A2 A1 A0
2
C Data (I2C_DAT) Register (D[7:0]/0x4344)
D6
2
EPSON
2
C module starts data transmission
2
C module sets the
D0
ACK
NACK
8 9
S1C17704 TECHNICAL MANUAL