8-Bit Osc1 Timer Interrupt - Epson S1C17704 Technical Manual

14.7 8-bit OSC1 Timer Interrupt

The T8OSC1 module is able to output an interrupt request signal to the interrupt controller (ITC) when a compare
match occurs.
Compare match interrupt
This interrupt request occurs when the count of the counter matches the set value of the compare data register
during count-up, and it sets the interrupt flag T8OIF (D0/T8OSC1_IFLG register) in the T8OSC1 module to 1.
∗ T8OIF: 8-bit OSC1 Timer Interrupt Flag in the 8-bit OSC1 Timer Interrupt Flag (T8OSC1_IFLG) Register
(D0/0x50c4)
Set the T8OIE (D0/T8OSC1_IMSK register) to 1 when using this interrupt. If T8OIE is set to 0 (default),
T8OIF will not be set to 1 and an interrupt request by this cause will not be sent to the ITC.
∗ T8OIE: 8-bit OSC1 Timer Interrupt Enable Bit in the 8-bit OSC1 Timer Interrupt Mask (T8OSC1_IMSK)
Register (D0/0x50c3)
If T8OIF is set to 1, the T8OSC1 module outputs the interrupt request signal to the ITC. The interrupt request
signal sets the 8-bit OSC1 timer interrupt flag in the ITC to 1 and an interrupt occurs if other interrupt
conditions meet the ITC and S1C17 Core settings.
The interrupt handler routine must reset (write 1 to) T8OIF in the T8OSC1 module, not the 8-bit OSC1 timer
interrupt flag in the ITC, to clear the cause of interrupt.
Note: To avoid occurrence of unnecessary interrupts, be sure to reset the T8OIF flag before the
compare match interrupt is enabled using T8OIE.
ITC registers for 8-bit OSC1 timer interrupt
When a compare match occurs according to the interrupt condition settings shown above, the 8-bit OSC1 timer
asserts the interrupt signal sent to the ITC.
To generate an 8-bit OSC1 timer interrupt, set the interrupt level and enable the interrupt using the ITC
registers.
The following shows the control bits for the 8-bit OSC1 timer interrupt in the ITC.
Interrupt flag in the ITC
∗ EIFT4: 8-bit OSC1 Timer Interrupt Flag in the Interrupt Flag (ITC_IFLG) Register (D4/0x4300)
Interrupt enable bit in the ITC
∗ EIEN4: 8-bit OSC1 Timer Interrupt Enable Bit in the Interrupt Enable (ITC_EN) Register (D4/0x4302)
Interrupt level setup bits in the ITC
∗ EILV4[2:0]: T8OSC1 Interrupt Level Bits in the External Interrupt Level Setup (ITC_ELV2) Register 2
(D[2:0]/0x430a)
Interrupt trigger mode select bit in the ITC (fixed at 1)
∗ EITG4: T8OSC1 Interrupt Trigger Mode Select Bit in the External Interrupt Level Setup (ITC_ELV2) Register 2
(D4/0x430a)
When a compare match whose interrupt is enabled in the T8OSC1 module occurs, EIFT4 is set to 1. If EIEN4
has been set to 1, the ITC sends an interrupt request to the S1C17 Core. To disable the 8-bit OSC1 timer
interrupt, set EIEN4 to 0. EIFT4 is always set to 1 by the interrupt signal sent from the T8OSC1 module,
regardless of how EIEN4 is set (even when set to 0).
EILV4[2:0] sets the interrupt level (0 to 7) of the 8-bit OSC1 timer interrupt.
S1C17704 TECHNICAL MANUAL
EPSON
14 8-BIT OSC1 TIMER (T8OSC1)
14-7