0X5346: Remc Interrupt Mask Register (Remc_Imsk) - Epson S1C17704 Technical Manual

0x5346: REMC Interrupt Mask Register (REMC_IMSK)

Register name Address Bit
REMC Interrupt 0x5346 D7–3 –
Mask Register (8 bits)
D2
(REMC_IMSK)
D1
D0
This register enables or disables the interrupt requests caused by a data length counter underflow, the rising edge of
the input signal, and the falling edge of the input signal, individually. Setting an interrupt enable bit to 1 enables the
interrupt request by the corresponding cause of interrupt; setting it to 0 disables the interrupt.
In addition, it is necessary to set the REMC interrupt enable bit in the ITC to interrupt enabled to actually generate
an interrupt.
D[7:3] Reserved
D2 REMFIE: Falling Edge Interrupt Enable Bit
Enables or disables the interrupt by detecting the falling edge of the input signal.
1 (R/W): Enable interrupt
0 (R/W): Disable interrupt (default)
D1 REMRIE: Rising Edge Interrupt Enable Bit
Enables or disables the interrupt by detecting the rising edge of the input signal.
1 (R/W): Enable interrupt
0 (R/W): Disable interrupt (default)
D0 REMUIE: Underflow Interrupt Enable Bit
Enables or disables the interrupt by a data length counter underflow.
1 (R/W): Enable interrupt
0 (R/W): Disable interrupt (default)
S1C17704 TECHNICAL MANUAL
Name Function
reserved
REMFIE Falling edge interrupt enable
REMRIE Rising edge interrupt enable
REMUIE Underflow interrupt enable
EPSON
21 REMOTE CONTROLLER (REMC)
Setting Init. R/W
–
1 Enable 0 Disable
1 Enable 0 Disable
1 Enable 0 Disable
Remarks
– – 0 when being read.
0 R/W
0 R/W
0 R/W
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