Processing When Multiple Interrupts Occur - Epson S1C17704 Technical Manual

6.3.4 Processing when Multiple Interrupts Occur

The ITC provides the ITC_ELVx and ITC_ILVx registers (0x4306 to 0x4314) to set an interrupt level (zero to
seven) for each cause of interrupt.
Vector No. Hardware interrupt
4 P0 port interrupt
5 P1 port interrupt
6 Stopwatch timer interrupt
7 Clock timer interrupt
8 8-bit OSC1 timer interrupt
9 SVD interrupt
10 LCD interrupt
11 PWM & capture timer interrupt
12 8-bit timer interrupt
13 16-bit timer Ch.0 interrupt
14 16-bit timer Ch.1 interrupt
15 16-bit timer Ch.2 interrupt
16 UART interrupt
17 Remote controller interrupt
18 SPI interrupt
2
19 I C interrupt
The highest interrupt level is 7 and the lowest is 0.
The set interrupt level is sent to the S1C17 Core at the same time the ITC sends an interrupt request and is used by
the S1C17 Core to disable subsequent interrupts that have the same or a lower interrupt level. (See Section 6.3.6 for
more information.)
At initial reset, the interrupt levels are all set to 0. The S1C17 Core does not accept an interrupt request whose
interrupt level is set to 0.
In the ITC, the interrupt level is used when two or more causes of interrupt occur simultaneously.
If two or more causes of interrupt that have been enabled by the interrupt enable bits occur simultaneously, the
cause of interrupt whose ITC_ELVx or ITC_ILVx register contains the highest value is allowed by the ITC to send
an interrupt request to the S1C17 Core.
If two or more causes of interrupt that have the same interrupt level occur, the interrupt with the smallest vector
number is processed first.
Other causes of interrupt are kept pending until all interrupts of higher priority are accepted by the S1C17 Core.
If another cause of interrupt of higher priority occurs during outputting an interrupt request signal, the ITC changes
the vector number and interrupt level to that of the new cause of interrupt. The first interrupt request is left pending.
S1C17704 TECHNICAL MANUAL
Table 6.3.4.1 Interrupt Level Setup Bits
Interrupt level setup bits
EILV0[2:0] (D[2:0]/ITC_ELV0 register)
EILV1[2:0] (D[10:8]/ITC_ELV0 register)
EILV2[2:0] (D[2:0]/ITC_ELV1 register)
EILV3[2:0] (D[10:8]/ITC_ELV1 register)
EILV4[2:0] (D[2:0]/ITC_ELV2 register)
EILV5[2:0] (D[10:8]/ITC_ELV2 register)
EILV6[2:0] (D[2:0]/ITC_ELV3 register)
EILV7[2:0] (D[10:8]/ITC_ELV3 register)
IILV0[2:0] (D[2:0]/ITC_ILV0 register)
IILV1[2:0] (D[10:8]/ITC_ILV0 register)
IILV2[2:0] (D[2:0]/ITC_ILV1 register)
IILV3[2:0] (D[10:8]/ITC_ILV1 register)
IILV4[2:0] (D[2:0]/ITC_ILV2 register)
IILV5[2:0] (D[10:8]/ITC_ILV2 register)
IILV6[2:0] (D[2:0]/ITC_ILV3 register)
IILV7[2:0] (D[10:8]/ITC_ILV3 register)
EPSON
6 INTERRUPT CONTROLLER (ITC)
Register address
0x4306
0x4306
0x4308
0x4308
0x430a
0x430a
0x430c
0x430c
0x430e
0x430e
0x4310
0x4310
0x4312
0x4312
0x4314
0x4314
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