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2
20 I
C
An interrupt request to the S1C17 Core is accepted only when all the conditions described below are met.
• The interrupt enable bit is set to 1.
• The IE (Interrupt Enable) bit of the PSR (Processor Status Register PSR) in the S1C17 Core is set to 1.
2
• The I
C interrupt has a higher interrupt level than the value that is set in the IL field of the PSR.
• No other cause of interrupt having higher priority, such as NMI, has occurred.
For details on these interrupt control registers, as well as the device operation when an interrupt has occurred,
see Chapter 6, "Interrupt Controller (ITC)."
Interrupt vector
The following shows the vector number and vector address for the I
Vector number: 19 (0x13)
Vector address: 0x804c
20-12
2
C interrupt:
EPSON
S1C17704 TECHNICAL MANUAL
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