Summary of Contents for Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03
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MF1574 - 01 CMOS 32 - BIT SINGLE CHIP MICROCOMPUTER S1C33L03 Technical Manual S1C33L03 PRODUCT PART S1C33L03 FUNCTION PART...
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No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any...
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S1C33L03 Technical Manual This manual describes the hardware specifications of the Seiko Epson original 32-bit microcomputer S1C33L03. S1C33L03 PRODUCT PART Describes the hardware specifications of the S1C33L03 except for details of the peripheral circuits. S1C33L03 FUNCTION PART Describes details of all the peripheral circuit blocks for the S1C33 Family microcomputers.
8.6.5 LCD Interface AC Characteristics ................A-96 8.7 Oscillation Characteristics....................A-107 8.8 PLL Characteristics ......................A-108 9 Package ..........................A-109 9.1 Plastic Package ........................A-109 10 Pad Layout .........................A-110 10.1 Pad Layout Diagram......................A-110 10.2 Pad Coordinate........................A-111 EPSON S1C33L03 TECHNICAL MANUAL...
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Appendix A <Reference> External Device Interface Timings.......... A-113 A.1 DRAM (70ns)........................A-114 A.2 DRAM (60ns)........................A-117 A.3 ROM and Burst ROM ......................A-121 A.4 SRAM (55ns) ........................A-123 A.5 SRAM (70ns) ........................A-125 A.6 8255A............................ A-127 Appendix B Pin Characteristics ................... A-128 EPSON S1C33L03 TECHNICAL MANUAL...
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Setting Device Type and Size ..................B-II-4-10 Setting SRAM Timing Conditions................. B-II-4-11 Setting Timing Conditions of Burst ROM ..............B-II-4-12 Bus Operation........................... B-II-4-13 Data Arrangement in Memory ..................B-II-4-13 Bus Operation of External Memory ................B-II-4-13 EPSON S1C33L03 TECHNICAL MANUAL...
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Power-Control Register Protection Flag ..................B-II-6-5 Operation in Standby Mode ....................... B-II-6-5 I/O Memory of Clock Generator ....................B-II-6-6 Programming Notes........................B-II-6-9 II-7 DBG (Debug Unit)......................B-II-7-1 Debug Circuit ..........................B-II-7-1 I/O Pins of Debug Circuit......................B-II-7-1 EPSON S1C33L03 TECHNICAL MANUAL...
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Switching Over the CPU Operating Clock ................B-III-6-3 Power-Control Register Protection Flag ................... B-III-6-4 Operation in Standby Mode ......................B-III-6-4 OSC1 Clock Output to External Devices .................. B-III-6-4 I/O Memory of Low-Speed (OSC1) Oscillation Circuit ............. B-III-6-5 Programming Notes........................B-III-6-8 EPSON S1C33L03 TECHNICAL MANUAL...
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I/O Control Register and I/O Modes................B-III-9-5 I/O Memory of I/O Ports....................B-III-9-6 Input Interrupt .......................... B-III-9-12 Port Input Interrupt....................... B-III-9-12 Key Input Interrupt ....................... B-III-9-14 Control Registers of the Interrupt Controller............... B-III-9-16 I/O Memory for Input Interrupts ................... B-III-9-18 Programming Notes.........................B-III-9-25 EPSON S1C33L03 TECHNICAL MANUAL...
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I/O Memory of HSDMA......................B-V-2-17 Programming Notes........................B-V-2-36 V-3 IDMA (Intelligent DMA)....................B-V-3-1 Functional Outline of IDMA ......................B-V-3-1 Programming Control Information....................B-V-3-1 IDMA Invocation .........................B-V-3-5 Operation of IDMA........................B-V-3-8 Linking............................B-V-3-12 Interrupt Function of Intelligent DMA ..................B-V-3-13 I/O Memory of Intelligent DMA....................B-V-3-14 Programming Notes........................B-V-3-17 EPSON S1C33L03 TECHNICAL MANUAL...
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Look-up Tables ......................B-VII-2-11 Frame Rates ......................B-VII-2-19 Other Settings ......................B-VII-2-20 Display Control ........................B-VII-2-21 Controlling LCD Power Up/Down................B-VII-2-21 Reading/Writing Display Data ................... B-VII-2-22 Setting the Display Start Address ................B-VII-2-22 Split-Screen Display ....................B-VII-2-23 EPSON viii S1C33L03 TECHNICAL MANUAL...
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Portrait Mode ......................B-VII-2-25 Power Save........................ B-VII-2-29 Controlling the GPIO Pins ..................B-VII-2-30 I/O Memory of LCD Controller....................B-VII-2-31 Programming Notes....................... B-VII-2-42 Precautions on Using ICD33....................B-VII-2-42 Examples of LCD Controller Setting Program..............B-VII-2-43 APPENDIX I/O MAP EPSON S1C33L03 TECHNICAL MANUAL...
1 OUTLINE 1 Outline The S1C33L03 is a Seiko Epson original 32-bit microcomputer with a built-in LCD controller. It features high speed, low power and low-voltage operation and is most suitable for portable equipment that needs display function, such as information terminals, E-mail terminals, electronic dictionaries.
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Note: The values of power consumption during execution were measured when a test program that consisted of 55% load instructions, 23% arithmetic operation instructions, 1% mac instruction, 12% branch instructions and 9% ext instruction was being continuously executed. Supply form QFP20-144pin plastic package, or chip. EPSON S1C33L03 PRODUCT PART...
Area 11 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "01" #CE11&12 * When CEFUNC[1:0] = "1x", this pin outputs #CE11+#CE12 signal. #CE3 – Area 3 chip enable – Read signal #EMEMRD – Read signal for internal ROM emulation memory EPSON S1C33L03 PRODUCT PART...
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Area read signal output for GA when CFEX3(D3/0x402DF) = "1" GPIO2: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and BREQEN(D2/0x39FFFD) = "0" EA10MD1 Pull-up Area 10 boot mode selection EA10MD1 EA10MD0 Mode EA10MD0 – External ROM mode Internal ROM mode EPSON S1C33L03 PRODUCT PART...
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I/O port when CFP07(D7/0x402D0) = "0" and CFEX7(D7/0x402DF) = "0" #SRDY1 (default) #DMAEND3 #SRDY1: Serial I/F Ch. 1 ready signal output when CFP07(D7/0x402D0) = "1" and CFEX5(D5/0x402DF) = "0" #DMAEND3: HSDMA Ch. 3 end-of-transfer signal output when CFEX7(D7/0x402DF) = "1" EPSON S1C33L03 PRODUCT PART...
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16-bit timer 0 event counter input when CFP10(D0/0x402D4) = "1", T8UF0 IOC10(D0/0x402D6) = "0" and CFEX1(D1/0x402DF) = "0" DST0 T8UF0: 8-bit timer 0 output when CFP10(D0/0x402D4) = "1", IOC10(D0/0x402D6) = "1" and CFEX1(D1/0x402DF) = "0" DST0: DST0 signal output when CFEX1(D1/0x402DF) = "1" (default) EPSON S1C33L03 PRODUCT PART...
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CFP24(D4/0x402D8) = "0" – P25: I/O port when CFP25(D5/0x402D8) = "0" (default) TM3: 16-bit timer 3 output when CFP25(D5/0x402D8) = "1" #SCLK2 #SCLK2: Serial I/F Ch. 2 clock input/output when SSCLK2(D2/0x402DB) = "1" and CFP25(D5/0x402D8) = "0" EPSON S1C33L03 PRODUCT PART...
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– P35: I/O port when CFP35(D5/0x402DC) = "0" (default) #BUSACK #BUSACK: Bus acknowledge output when CFP35(D5/0x402DC) = "1" and GPIO1 CFP34(D4/0x402DC) = "1" GPIO1: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and BREQEN(D2/0x39FFFD) = "0" EPSON A-10 S1C33L03 PRODUCT PART...
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1: CPU clock = bus clock 1, 0: CPU clock = bus clock #NMI Pull-up NMI request input pin #RESET Pull-up Initial reset input pin Note: "#" in the pin names indicates that the signal is low active. EPSON S1C33L03 PRODUCT PART A-11...
10 V pins. Be sure to supply the operating voltage to all the pins. Do not open any of them. The operating clock frequency range (OSC3) is 5 MHz to 50 MHz with this voltage. EPSON A-12 S1C33L03 PRODUCT PART...
Noise on the analog power lines decrease the A/D converting precision, so use a stabilized power supply and make the board pattern with consideration given to that. EPSON S1C33L03 PRODUCT PART A-13...
The S1C33L03 does not have a built-in ROM. The boot address is fixed at 0x0C00000, and so external ROM/Flash should be used in Area 10. For setting up Area 10, refer to the "BCU (Bus Control Unit)" in "S1C33L03 FUNCTION PART" in this manual. EPSON A-14 S1C33L03 PRODUCT PART...
The S1C33L03 has a built-in 8KB RAM. The RAM is allocated to Area 0, address 0x0000000 to address 0x0001FFF. The internal RAM is a 32-bit sized device and data can be read/written in 1 cycle regardless of data size (byte, half- word or word). EPSON S1C33L03 PRODUCT PART A-15...
2, 4, 16 or 256-level (1, 2, 4 or 8 bit-per-pixel) color display Resolution examples: 640 480 pixels with 1bpp color depth 640 240 pixels with 2bpp color depth 320 240 pixels with 4bpp color depth 240 160 pixels with 8bpp color depth EPSON A-16 S1C33L03 PRODUCT PART...
0, 1: Initial values that are set at initial reset. (However, the registers for the bus and input/output ports are not initialized at hot start.) Not initialized at initial reset. –: Not set in the circuit. EPSON S1C33L03 PRODUCT PART A-17...
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1 On 0 Off P8TS02 8-bit timer 0 P8TS0[2:0] Division ratio : selected by P8TS01 clock division ratio selection /256 Prescaler clock select P8TS00 /128 register (0x40181) 8-bit timer 0 can generate the DRAM refresh clock. EPSON A-18 S1C33L03 PRODUCT PART...
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Clock timer 0040154 D7–6 – reserved – – – 0 when being read. second TCMD5 Clock timer second counter data 0 to 59 seconds register TCMD4 TCMD5 = MSB TCMD3 TCMD0 = LSB TCMD2 TCMD1 TCMD0 EPSON S1C33L03 PRODUCT PART A-19...
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D7–5 – reserved – – – 0 when being read. TCCN4 Clock timer day comparison data 0 to 31 days Compared with comparison TCCN3 TCCN4 = MSB TCND[4:0]. register TCCN2 TCCN0 = LSB TCCN1 TCCN0 EPSON A-20 S1C33L03 PRODUCT PART...
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Watchdog 0040171 D7–2 – – – – – 0 when being read. timer enable Watchdog timer enable 1 NMI enabled 0 NMI disabled register – – – – – 0 when being read. EPSON S1C33L03 PRODUCT PART A-23...
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Writing 10010110 (0x96) protect register CLGP6 removes the write protection of CLGP5 the power control register CLGP4 (0x40180) and the clock option CLGP3 register (0x40190). CLGP2 Writing another value set the CLGP1 write protection. CLGP0 EPSON A-24 S1C33L03 PRODUCT PART...
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1 Inverted 0 Direct Valid only in IRRL0 Ch.0 IrDA I/F input logic inversion 1 Inverted 0 Direct asynchronous mode. IRMD01 Ch.0 interface mode selection IRMD0[1:0] I/F mode IRMD00 reserved IrDA 1.0 reserved General I/F EPSON S1C33L03 PRODUCT PART A-25...
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OER2 Ch.2 overrun error flag 1 Error 0 Normal Reset by writing 0. TDBE2 Ch.2 transmit data buffer empty 1 Empty 0 Buffer full RDBF2 Ch.2 receive data buffer full 1 Buffer full 0 Empty EPSON A-26 S1C33L03 PRODUCT PART...
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1 Inverted 0 Direct Valid only in IRRL3 Ch.3 IrDA I/F input logic inversion 1 Inverted 0 Direct asynchronous mode. IRMD31 Ch.3 interface mode selection IRMD3[1:0] I/F mode IRMD30 reserved IrDA 1.0 reserved General I/F EPSON S1C33L03 PRODUCT PART A-27...
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Reset by writing 0. A/D sampling 0040245 D7–2 – – – – – 0 when being read. register Input signal sampling time setup ST[1:0] Sampring time Use with 9 clocks. 9 clocks 7 clocks 5 clocks 3 clocks EPSON A-28 S1C33L03 PRODUCT PART...
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0 when being read. interrupt P16T52 16-bit timer 5 interrupt level 0 to 7 priority register P16T51 P16T50 – reserved – – – 0 when being read. P16T42 16-bit timer 4 interrupt level 0 to 7 P16T41 P16T40 EPSON S1C33L03 PRODUCT PART A-29...
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0 when being read. interrupt PP7L2 Port input 7 interrupt level 0 to 7 priority register PP7L1 PP7L0 – reserved – – – 0 when being read. PP6L2 Port input 6 interrupt level 0 to 7 PP6L1 PP6L0 EPSON A-30 S1C33L03 PRODUCT PART...
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– – – 0 when being read. clock timer, Port input 7 1 Enabled 0 Disabled A/D interrupt Port input 6 enable register Port input 5 Port input 4 ECTM Clock timer EADE A/D converter EPSON S1C33L03 PRODUCT PART A-31...
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0 when being read. clock timer, A/D Port input 7 1 Factor is 0 No factor is interrupt factor Port input 6 generated generated flag register Port input 5 Port input 4 FCTM Clock timer FADE A/D converter EPSON A-32 S1C33L03 PRODUCT PART...
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DEP4 Port input 4 register – reserved – – – 0 when being read. DEADE A/D converter 1 IDMA 0 IDMA DESTX1 SIF Ch.1 transmit buffer empty enabled disabled DESRX1 SIF Ch.1 receive buffer full EPSON S1C33L03 PRODUCT PART A-33...
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IDMA enable register set method 1 Set only 0 RD/WR register selection IDMAONLY IDMA request register set method 1 Set only 0 RD/WR selection RSTONLY Interrupt factor flag reset method 1 Reset only 0 RD/WR selection EPSON A-34 S1C33L03 PRODUCT PART...
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K65 input port data – K64D K64 input port data – K63D K63 input port data – K62D K62 input port data – K61D K61 input port data – K60D K60 input port data – EPSON S1C33L03 PRODUCT PART A-35...
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P16 I/O port data 1 High 0 Low P15D P15 I/O port data P14D P14 I/O port data P13D P13 I/O port data P12D P12 I/O port data P11D P11 I/O port data P10D P10 I/O port data EPSON S1C33L03 PRODUCT PART A-37...
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P34 I/O control indicates the values IOC33 P33 I/O control of the I/O control IOC32 P32 I/O control signals of the ports IOC31 P31 I/O control when it is read. (See IOC30 P30 I/O control detailed explanation.) EPSON A-38 S1C33L03 PRODUCT PART...
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1 8 bits 0 16 bits A14DF1 Areas 14–13 A14DF[1:0] Number of cycles A14DF0 output disable delay time – reserved – – – 0 when being read. A14WT2 Areas 14–13 wait control A14WT[2:0] Wait cycles A14WT1 A14WT0 EPSON S1C33L03 PRODUCT PART A-39...
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1 8 bits 0 16 bits A8DF1 Areas 8–7 A8DF[1:0] Number of cycles A8DF0 output disable delay time – reserved – – – 0 when being read. A8WT2 Areas 8–7 wait control A8WT[2:0] Wait cycles A8WT1 A8WT0 EPSON A-40 S1C33L03 PRODUCT PART...
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DF–1 – reserved – – – Undefined in read. DMA Ch.3 (HW) trigger flag HS3_TF Ch.3 trigger flag clear (writing) 1 Clear 0 No operation register Ch.3 trigger flag status (reading) 1 Set 0 Cleared EPSON A-58 S1C33L03 PRODUCT PART...
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SDRTRAS2 SDRAM t spec SDRTRAS[2:0] Number of clocks timing set-up SDRTRAS1 register 1 SDRTRAS0 D4–3 SDRTRP1 SDRAM t spec SDRTRP[1:0] Number of clocks SDRTRP0 D2–0 SDRTRC2 SDRAM t spec SDRTRC[2:0] Number of clocks SDRTRC1 SDRTRC0 EPSON S1C33L03 PRODUCT PART A-59...
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039FFCA SDRMRS SDRAM mode register set flag 1 Not finished 0 Done status register SDRSRM SDRAM current refresh mode 1 Auto refresh 0 Self refresh D5–0 – reserved – – – 0 when being read. EPSON A-60 S1C33L03 PRODUCT PART...
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V resolution (lines) - 1 register 1 LDVSIZE8 (high-order 2 bits) Horizontal 039FFE7 D7–5 – reserved – – – 0 when being read. non-display HNDP4 Horizontal non-display period Non-display period (pixels) period register HNDP3 HNDP2 HNDP1 HNDP0 EPSON S1C33L03 PRODUCT PART A-61...
Even during operation using the high-speed (OSC3) oscillation clock, power reduction can also be achieved through the use of a system clock derived from the OSC3 clock by dividing it (1/1, 1/2, 1/4, or 1/8). EPSON S1C33L03 PRODUCT PART A-65...
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8-bit timer 5 clock control P8TON5(D7)/8-bit timer 4/5 clock control register(0x40145) 8-bit timer 5 Run/Stop PTRUN5(D0)/8-bit timer 5 control register(0x40178) STOP STOP A/D converter clock control PSONAD(D3)/A/D clock control register(0x4014F) A/D conversion enable ADE(D2)/A/D enable register(0x40244) STOP STOP EPSON A-66 S1C33L03 PRODUCT PART...
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This may cause damage of the LCD panel if the clock supply to the LCD controller is stopped at the same time. Therefore, do not stop the clock supply for 1 frame cycles or more after setting the LCD controller to power save mode. EPSON S1C33L03 PRODUCT PART A-67...
33 MHz (Max.) Gate capacitor 10 pF Drain capacitor 10 pF Feedback resistor Resistor 4.7 k Capacitor 100 pF Capacitor 5 pF Note: The above table is simply an example, and is not guaranteed to work. EPSON A-68 S1C33L03 PRODUCT PART...
• Sudden power supply variation due to noise may cause malfunction. Consider the following points to prevent this: (1) The power supply should be connected to the V and AV pins with patterns as short and large as possible. In particular, the power supply for AV affects A/D conversion precision. EPSON S1C33205 PRODUCT PART A-69...
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Do not arrange a high-speed signal line especially near circuits that are sensitive to noise such as the oscillation unit and analog input unit. Prohibited pattern K60 (AD0) OSC4 OSC3 Large current signal line High-speed signal line Large current signal line High-speed signal line EPSON A-70 S1C33205 PRODUCT PART...
High-level output current 1 pin Total of all pins Low-level output current 1 pin Total of all pins Analog power voltage -0.3 to +7.0 Analog input voltage -0.3 to AV +0.3 Storage temperature -65 to +150 °C EPSON S1C33L03 PRODUCT PART A-71...
– 32.768 – OSC1 Operating temperature °C Input rise time (normal input) – – Input fall time (normal input) – – Input rise time (schmitt input) – – Input fall time (schmitt input) – – EPSON A-72 S1C33L03 PRODUCT PART...
Other than DSIO DSIO Pull-down resistor (ICEMD) Input pin capacitance – – f=1MHz, V Output pin capacitance – – f=1MHz, V I/O pin capacitance – – f=1MHz, V Note: See Appendix B for pin characteristics. EPSON S1C33L03 PRODUCT PART A-73...
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Other than DSIO DSIO Pull-down resistor (ICEMD) Input pin capacitance – – f=1MHz, V Output pin capacitance – – f=1MHz, V I/O pin capacitance – – f=1MHz, V Note: See Appendix B for pin characteristics. EPSON A-74 S1C33L03 PRODUCT PART...
1: The values of current consumption while the CPU is operating were measured when a test program that consists of 55% load instructions, 23% arithmetic operation instructions, 1% mac instruction, 12% branch instructions and 9% ext instruction is being executed in the built-in ROM continuously. 2: The LCD controller is included. EPSON S1C33L03 PRODUCT PART A-75...
V[000]h = Ideal voltage at zero-scale point (=0.5LSB) 1LSB = V'[000]h = Actual voltage at zero-scale point V[3FF]h = Ideal voltage at full-scale point (=1022.5LSB) V'[3FF]h - V'[000]h 1LSB' = V'[3FF]h = Actual voltage at full-scale point EPSON A-76 S1C33L03 PRODUCT PART...
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[LSB] 1LSB' Actual conversion characteristic Ideal conversion characteristic V'[000]h Analog input Differential linearity error Ideal conversion characteristic Actual conversion characteristic V'[N]h V'[N]h - V'[N-1]h Differential linearity error E - 1 [LSB] 1LSB' V'[N-1]h Analog input EPSON S1C33L03 PRODUCT PART A-77...
High level = 1/2 V Low level = 1/2 V Input signal waveform: Rise time (10% 90% V ) 5 ns Fall time (90% 10% V ) 5 ns Output load capacitance: C = 50 pF EPSON A-78 S1C33L03 PRODUCT PART...
Item Symbol Min. Max. Unit BCLK clock output duty 3) 2.0 V single power source (Unless otherwise specified: V =2.0V 0.2V, V =0V, Ta=-40°C to +85°C) Item Symbol Min. Max. Unit BCLK clock output duty EPSON S1C33L03 PRODUCT PART A-79...
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Write data delay time (2) WDD2 Write data hold time note 1) This applies to the #BSH and #BSL timings. 2) This applies to the #GAAS and #GARD timings. 3) This applies to the #GAAS timing. EPSON A-80 S1C33L03 PRODUCT PART...
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Write signal pulse width (1+WC)-10 3) 2.0 V single power source (Unless otherwise specified: V =2.0V 0.2V, V =0V, Ta=-40°C to +85°C) Item Symbol Min. Max. Unit Write signal delay time (2) WRD2 Write signal pulse width (1+WC)-20 EPSON S1C33L03 PRODUCT PART A-81...
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#CAS signal delay time (2) CASD2 #CAS signal pulse width (0.5+WC)-20 CASW Read signal delay time (3) RDD3 Read signal pulse width (2) (2+WC)-20 RDW2 Write signal delay time (3) WRD3 Write signal pulse width (2) (2+WC)-20 WRW2 EPSON A-82 S1C33L03 PRODUCT PART...
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(Unless otherwise specified: V =2.0V 0.2V, V =0V, Ta=-40°C to +85°C) Item Symbol Min. Max. Unit Column address access time (1.5+WC)-60 ACCE #RAS access time (2+WC)-60 RACE #CAS access time (1+WC)-60 CACE Read data setup time RDS2 EPSON S1C33L03 PRODUCT PART A-83...
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#SDWE signal delay time (2) T+11 (WEDx2)p Read data setup time (14) (RDSx2) Read data hold time (RDHx2) Write data delay time (WDDx2) Write data hold time T+11 (WDHx2) Note: "T" indicates one cycle time of the CPU clock. EPSON A-84 S1C33L03 PRODUCT PART...
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=0V, Ta=-40°C to +85°C) Item Symbol Min. Max. Unit #BUSREQ signal setup time BRQS #BUSREQ signal hold time BRQH #BUSACK signal output delay time BAKD High-impedance output delay time Output high-impedance delay time #NMI pulse width NMIW EPSON S1C33L03 PRODUCT PART A-85...
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=2.0V 0.2V, V =0V, Ta=-40°C to +85°C) Item Symbol Min. Max. Unit Input data setup time INPS Input data hold time INPH Output data delay time OUTD K-port interrupt SLEEP, HALT2 mode KINW input pulse width Others EPSON A-86 S1C33L03 PRODUCT PART...
8.6.4 C33 Block AC Characteristic Timing Charts Clock (1) When an external clock is input (in x1 speed mode): OSC3 C3ED (High-speed clock) BCLK (Clock output) (2) When the high-speed oscillation circuit is used for the operating clock: BCLK (Clock output) EPSON S1C33L03 PRODUCT PART A-87...
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SRAM read cycle (when a wait cycle is inserted) (wait cycle) (last cycle) BCLK A[23:0] #CEx (C1 only) RDD1 RDD2 CEAC1 ACC1 RDAC1 D[15:0] #WAIT is measured with respect to the first signal change (negation) from among the #RD, #CEx and A[23:0] signals. EPSON A-88 S1C33L03 PRODUCT PART...
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#HCAS/ #LCAS RDD1 RDD3 RDW2 CACF ACCF RACF ACCF D[15:0] WRD1 WRD3 WRW2 WDD1 WDD2 WDD2 D[15:0] is measured with respect to the first signal change (negation) of either the #RD or the A[23:0] signals. EPSON A-90 S1C33L03 PRODUCT PART...
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RDD1 RDD3 RDW2 ACCE CACE RACE ACCE D[15:0] WRD1 WRD3 WRW2 WDD1 WDD2 WDD2 D[15:0] is measured with respect to the first signal change from among the #RD (negation), #RASx (negation) and #CAS (fall) signals. EPSON S1C33L03 PRODUCT PART A-91...
Power Save active to LCDPWR inactive Frame Power Save active to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY Frame inactive LPWREN = "1" to LCDPWR active Frame (when FP signals are active) LPWREN = "0" to LCDPWR inactive Frame EPSON A-96 S1C33L03 PRODUCT PART...
Operating temperature =2.7V to 3.6V °C =1.9V to 2.2V °C =1.8V to 2.2V °C #1 Q11C02RX: Crystal resonator made by Seiko Epson #2 "C =15pF" includes board capacitance. (Unless otherwise specified: V =3.3V, V =0V, crystal=Q11C02RX 32.768kHz, =20M , C =15pF , Ta=25°C)
Symbol Condition Min. Typ. Max. Unit Jitter (peak jitter) Lockup time #1 Q3204DC: Crystal oscillator made by Seiko Epson (Unless otherwise specified: V =2.0V 0.2V, V =0V, crystal oscillator=Q3204DC =4.7k , C =100pF, C =5pF, Ta=-40°C to +85°C) Item Symbol Condition Min.
This thermal resistance is a value under the condition that the measured device is hanging in the air and has no air-cooling. Thermal resistance greatly varies according to the mounting condition on the board and air- cooling condition. EPSON S1C33L03 PRODUCT PART A-109...
Conditions such as the output delay time of the device, delay due to wiring and load capacitance, and input setup time are not considered. • The described contents are reference data and cannot be guaranteed to work. EPSON S1C33L03 PRODUCT PART A-113...
Fast-page mode #CAS precharge time – Access time after #CAS precharge <Refresh cycle> – #CAS setup time – #CAS hold time – #RAS precharge #CAS hold time 10000 #RAS pulse width (only in refresh cycle) EPSON A-114 S1C33L03 PRODUCT PART...
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COL #1 COL #2 #RAS #CAS D[15:0](RD) RD data RD data D[15:0](WR) WR data WR data DRAM: 70ns, CPU: 33MHz, CAS-before-RAS refresh cycle RPC delay Fixed Refresh RAS pulse width RAS precharge BCLK #RAS #CAS EPSON S1C33L03 PRODUCT PART A-115...
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COL #1 COL #2 #RAS #CAS D[15:0](RD) RD data RD data D[15:0](WR) WR data WR data DRAM: 70ns, CPU: 25/20MHz, CAS-before-RAS refresh cycle RPC delay Fixed Refresh RAS pulse width RAS precharge BCLK #RAS #CAS EPSON A-116 S1C33L03 PRODUCT PART...
Fast-page mode #CAS precharge time – Access time after #CAS precharge <Refresh cycle> – #CAS setup time – #CAS hold time – #RAS precharge #CAS hold time 10000 #RAS pulse width (only in refresh cycle) EPSON S1C33L03 PRODUCT PART A-117...
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COL #1 COL #2 #RAS #CAS D[15:0](RD) RD data RD data D[15:0](WR) WR data WR data DRAM: 60ns, CPU: 33MHz, CAS-before-RAS refresh cycle RPC delay Fixed Refresh RAS pulse width RAS precharge BCLK #RAS #CAS EPSON A-118 S1C33L03 PRODUCT PART...
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COL #1 COL #2 #RAS #CAS D[15:0](RD) RD data RD data D[15:0](WR) WR data WR data DRAM: 60ns, CPU: 25MHz, CAS-before-RAS refresh cycle RPC delay Fixed Refresh RAS pulse width RAS precharge BCLK #RAS #CAS EPSON S1C33L03 PRODUCT PART A-119...
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COL #1 COL #2 #RAS #CAS D[15:0](RD) RD data RD data D[15:0](WR) WR data WR data DRAM: 60ns, CPU: 20MHz, CAS-before-RAS refresh cycle RPC delay Fixed Refresh RAS pulse width RAS precharge BCLK #RAS #CAS EPSON A-120 S1C33L03 PRODUCT PART...
3 If the data hold time that can be set is not sufficient for the device, secure it by connecting a bus repeater to the external data bus D[15:0] or by inserting a latch at the output side of the external system interface. EPSON S1C33L03 PRODUCT PART...
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The following table lists output current characteristics. Output current (I 5.0 V 3.3 V 2.0 V Type1 3 mA 2 mA 0.6 mA Type2 – 6 mA 2 mA Type3 12 mA 12 mA 4 mA EPSON A-130 S1C33L03 PRODUCT PART...
I OUTLINE: INTRODUCTION I-1 INTRODUCTION The Function Part gives a detailed description of the various function blocks built into the Seiko Epson original 32-bit microcomputer S1C33L03. The S1C33L03 employs a RISC type CPU, and has a powerful instruction set capable of compilation into compact code, despite the small CPU core size.
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I OUTLINE: INTRODUCTION THIS PAGE IS BLANK. EPSON B-I-1-2 S1C33L03 FUNCTION PART...
C33 Core Block C33_ADC C33_PERI Pads (A/D converter) (Prescaler, 8-bit timer, 16-bit timer, Clock timer, Serial interface, Ports) C33 Analog Block C33 Peripheral Block Figure 2.1 Block Configuration Note: Internal ROM is not provided in the S1C33L03. EPSON S1C33L03 FUNCTION PART B-I-2-1...
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The LCD Controller Block provides LCD control signals for a 4- or 8-bit color/monochrome LCD panel. C33 Memory Block The S1C33L03 contains an 8KB of SRAM as the internal memory. For details of the blocks, refer to the respective section in this manual. EPSON B-I-2-2 S1C33L03 FUNCTION PART...
Write (low byte) signal when SBUSST(D3/0x4812E) = "0" (default) #WR: Write signal when SBUSST(D3/0x4812E) = "1" #WE: DRAM write signal #WRH – #WRH: Write (high byte) signal when SBUSST(D3/0x4812E) = "0" (default) #BSH #BSH: Bus strobe (high byte) signal when SBUSST(D3/0x4812E) = "1" EPSON S1C33L03 FUNCTION PART B-I-3-1...
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Area read signal output for GA when CFEX3(D3/0x402DF) = "1" GPIO2: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and BREQEN(D2/0x39FFFD) = "0" EA10MD1 Pull-up Area 10 boot mode selection EA10MD1 EA10MD0 Mode EA10MD0 – External ROM mode Internal ROM mode EPSON B-I-3-2 S1C33L03 FUNCTION PART...
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I/O port when CFP07(D7/0x402D0) = "0" and CFEX7(D7/0x402DF) = "0" #SRDY1 (default) #DMAEND3 #SRDY1: Serial I/F Ch. 1 ready signal output when CFP07(D7/0x402D0) = "1" and CFEX5(D5/0x402DF) = "0" #DMAEND3: HSDMA Ch. 3 end-of-transfer signal output when CFEX7(D7/0x402DF) = "1" EPSON S1C33L03 FUNCTION PART B-I-3-3...
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16-bit timer 0 event counter input when CFP10(D0/0x402D4) = "1", T8UF0 IOC10(D0/0x402D6) = "0" and CFEX1(D1/0x402DF) = "0" DST0 T8UF0: 8-bit timer 0 output when CFP10(D0/0x402D4) = "1", IOC10(D0/0x402D6) = "1" and CFEX1(D1/0x402DF) = "0" DST0: DST0 signal output when CFEX1(D1/0x402DF) = "1" (default) EPSON B-I-3-4 S1C33L03 FUNCTION PART...
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CFP24(D4/0x402D8) = "0" – P25: I/O port when CFP25(D5/0x402D8) = "0" (default) TM3: 16-bit timer 3 output when CFP25(D5/0x402D8) = "1" #SCLK2 #SCLK2: Serial I/F Ch. 2 clock input/output when SSCLK2(D2/0x402DB) = "1" and CFP25(D5/0x402D8) = "0" EPSON S1C33L03 FUNCTION PART B-I-3-5...
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– P35: I/O port when CFP35(D5/0x402DC) = "0" (default) #BUSACK #BUSACK: Bus acknowledge output when CFP35(D5/0x402DC) = "1" and GPIO1 CFP34(D4/0x402DC) = "1" GPIO1: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and BREQEN(D2/0x39FFFD) = "0" EPSON B-I-3-6 S1C33L03 FUNCTION PART...
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1: CPU clock = bus clock 1, 0: CPU clock = bus clock #NMI Pull-up NMI request input pin #RESET Pull-up Initial reset input pin Note: "#" in the pin names indicates that the signal is low active. EPSON S1C33L03 FUNCTION PART B-I-3-7...
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I OUTLINE: LIST OF PINS THIS PAGE IS BLANK. EPSON B-I-3-8 S1C33L03 FUNCTION PART...
C33 Core Block C33_ADC C33_PERI Pads (A/D converter) (Prescaler, 8-bit timer, 16-bit timer, Clock timer, Serial interface, Ports) C33 Analog Block C33 Peripheral Block Figure 1.1 Core Block Note: Internal ROM is not provided in the S1C33L03. EPSON S1C33L03 FUNCTION PART B-II-1-1...
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II CORE BLOCK: INTRODUCTION THIS PAGE IS BLANK. EPSON B-II-1-2 S1C33L03 FUNCTION PART...
Note that SLEEP mode cannot be canceled with an interrupt factor except for reset and NMI if the PSR is set into interrupt disabled status. EPSON B-II-2-2 S1C33L03 FUNCTION PART...
In the debug mode, the OSC3 clock is used as the CPU operating clock. Therefore, do not stop the high-speed (OSC3) oscillation circuit when using the debugging functions. Furthermore, only the CPU and BCU operate in the debug mode, and other internal peripheral circuits (except the oscillation circuit) stop operating. EPSON S1C33L03 FUNCTION PART B-II-2-3...
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Edge (rising or falling) or level (High or Low) 71(Base+11C) Port input interrupt 7 Edge (rising or falling) or level (High or Low) Base = Set value in the TTBR register (0x48134 to 0x48137); 0xC00000 by default. B-II EPSON S1C33L03 FUNCTION PART B-II-2-5...
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II CORE BLOCK: CPU AND OPERATING MODE THIS PAGE IS BLANK. EPSON B-II-2-6 S1C33L03 FUNCTION PART...
#NMI must be set to high longer than #NMI must be set to low longer than the reset pulse width. the reset pulse width. (1) Cold start (2) Hot start Figure 3.1 Setup of #RESET and #NMI Pins EPSON S1C33L03 FUNCTION PART B-II-3-1...
To reset the chip when the high-speed (OSC3) oscillation circuit is in off status, the pulse width must be extended until the oscillation stabilizes similarly to the power-on reset. Be aware that a short reset pulse may cause an operation error. EPSON B-II-3-2 S1C33L03 FUNCTION PART...
(cold start or hot start). Therefore, it is necessary to set up the peripheral circuit conditions. Refer to the I/O maps or explanation of each peripheral circuit section for initial settings of the peripheral circuits. EPSON S1C33L03 FUNCTION PART B-II-3-3...
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II CORE BLOCK: INITIAL RESET THIS PAGE IS BLANK. EPSON B-II-3-4 S1C33L03 FUNCTION PART...
/ Serial I/F Ch. 3 clock input/output / SDRAM data (low byte) input/output mask signal output #X2SPD CPU - BCLK clock ratio 1: CPU clock = Bus clock, 0: CPU clock = Bus clock x 2 EA10MD[1:0] Area 10 boot mode selection 11: External ROM, 10: Internal ROM EPSON S1C33L03 FUNCTION PART B-II-4-1...
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The user logic can also be used as input ports with these signals. The internal bus signals are available when an internal access area is set using the BCU register. The bus conditions can be programmed using the BCU registers similar to the external bus. EPSON B-II-4-2 S1C33L03 FUNCTION PART...
1 In the #BSL system, the A0 and #WRH pin functions change according to the endian selected (little endian or big endian). When using DRAM, the #CE output pins in areas 7–8 (areas 13–14) function as the #RAS1–2 (#RAS3–4) pins. EPSON S1C33L03 FUNCTION PART B-II-4-3...
Note: Addresses 0x39FFC0–0x39FFCD in Area 6 are reserved as the internal memory area for the control I/O memory of the SDRAM controller. Pay attention to this area since it must be accessed when controlling the SDRAM self-refresh mode or other SDRAM functions. EPSON B-II-4-4 S1C33L03 FUNCTION PART...
Area 4 (#CE4) 0x01FFFFF 0x03FFFFF External I/O (16-bit device) SRAM type SRAM type 0x0380000 External memory 1 (1MB) 8 or 16 bits 0x037FFFF External I/O (8-bit device) 0x0100000 0x0300000 CEFUNC = "00" CEFUNC = "01" EPSON S1C33L03 FUNCTION PART B-II-4-5...
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The P30 and P34 terminals are set for the general I/O ports at initial reset. The P30 and P34 terminals are shared with the #WAIT input and the #BUSREQ input, respectively. Therefore, when using the #WAIT and #BUSREQ signals, these terminals cannot be used for #CE4+#CE5 and #CE6 outputs. EPSON B-II-4-6 S1C33L03 FUNCTION PART...
CFEX3 (D3)/Port function extension register (0x402DF) = "1" These signals are common used to all the above areas, so when two or more areas are selected to output the exclusive signal, OR condition is applied. EPSON S1C33L03 FUNCTION PART B-II-4-7...
Area 3 is reserved for S1C33 middleware. To use this area, external emulation memory is used. When external emulation memory is used, A3EEN (DB/0x48130) must be set to "1". Table 4.8 Area 3 Mode Selection A3EEN Area 3 mode Emulation mode Unused EPSON S1C33L03 FUNCTION PART B-II-4-9...
Note: The BCU supports 16-bit burst ROM. Therefore, when connecting burst ROM to area 10 or area 9, do not set the device size to 8 bits (A10SZ = "1"). For differences in bus operation due to the device size and access data size, refer to "Bus Operation of External Memory". EPSON B-II-4-10 S1C33L03 FUNCTION PART...
If the number of wait cycles set is 2 or more, the bus cycle is actually extended. In this case, the bus write cycle consists of [number of wait cycles + 1], as in the case of read cycles (providing that there is no external wait). EPSON S1C33L03 FUNCTION PART B-II-4-11...
RBST8 (DD) / Bus control register (0x4812E) is used for this selection. The eight-consecutive-burst mode is selected by writing "1" to RBST8 and the four-consecutive-burst mode is selected by setting the bit to "0". At cold start, the four-consecutive-burst mode is set by default. EPSON B-II-4-12 S1C33L03 FUNCTION PART...
(1) For data reads, the operation is as shown in the figure below. (2) For little-endian data writes, read A0 as #BSC, and #WRH as #BSH. (3) For big-endian data writes, read A0 as #BSL, and #WRL as #BSH. EPSON S1C33L03 FUNCTION PART B-II-4-13...
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Destination (general-purpose register) Bus operation Sign or Zero extension Byte 1 Byte 0 Data bus #WRH #WRL Byte 1 Byte 0 A[1:0]= 0 Source (16-bit device) Figure 4.8 Half-word Data Reading from a 16-bit Device EPSON B-II-4-14 S1C33L03 FUNCTION PART...
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Byte 1 Byte 0 Data bus #WRH #WRL Byte 3 Ignored Byte 2 Ignored A[1:0]=00 A[1:0]=01 A[1:0]=10 A[1:0]=11 Byte 1 Ignored Source (8-bit device) Byte 0 Ignored Figure 4.12 Word Data Reading from an 8-bit Device EPSON S1C33L03 FUNCTION PART B-II-4-15...
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Source (8-bit device) Big-endian Destination (general-purpose register) Bus operation Sign or Zero extension Byte 0 Data bus #WRH #WRL Byte 0 Ignored A[1:0]= Source (8-bit device) Figure 4.16 Byte Data Reading from an 8-bit Device EPSON B-II-4-16 S1C33L03 FUNCTION PART...
SD_CLK (SDRCLK = "1") SD_CLK (SDRCLK = "0") SDCKE Self refresh 1 Access to the internal RAM 2 Access to the external memory (other than SDRAM) 3 Access to the SDRAM Figure 4.17 Clock System EPSON S1C33L03 FUNCTION PART B-II-4-17...
(high level), the read cycle is terminated. Note: Insertion of wait cycles via the #WAIT pin is possible only when the device for bus conditions is set for SRAM, and SWAITE (D0) / Bus control register (0x4812E) is enabled for waiting. EPSON S1C33L03 FUNCTION PART B-II-4-19...
With an output disable cycle, there is normally a gap between one read cycle and the next. Note, however, that this output disable cycle is not inserted in the case of consecutive reads in a memory area for which the same chip enable signal is output. EPSON B-II-4-20 S1C33L03 FUNCTION PART...
Figure 4.23 Byte Write Cycle with No Wait (A0 system, little endian) BCLK addr A[23:0] #CExx #BSH #BSL #WRL Undefined Valid D[15:8] Valid Undefined D[7:0] Figure 4.24 Byte Write Cycle with No Wait (#BSL system, little endian) EPSON S1C33L03 FUNCTION PART B-II-4-21...
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In this case, the bus write cycle consists of [number of wait cycles + 1], as in the case of read cycles (providing that there is no external wait). EPSON B-II-4-22 S1C33L03 FUNCTION PART...
If area 10 or 9 is set for burst ROM, a SRAM write cycle is executed when a write to that area is attempted. In this case, wait cycles via the #WAIT pin can be inserted. EPSON S1C33L03 FUNCTION PART...
(256K bytes) 5 DRAM (4M) DRAM (4M) 8M bits (1M bytes) 6 DRAM (16M) DRAM (16M) 32M bits (4M bytes) Also, the S1C33L03 provides an SDRAM direct interface. Refer to "VI SDRAM Controller Block" for details. EPSON B-II-4-24 S1C33L03 FUNCTION PART...
If the successive RAS mode is suspended, a precharge cycle is inserted before the next bus cycle begins. Note: When using the successive RAS mode, always be sure to use #DRD for the read signal and #DWE for the low-byte write signal. EPSON S1C33L03 FUNCTION PART B-II-4-25...
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RPC2 to "0". If RPC1 is switched over when RPC2 = "1" (refresh enabled), an undesirable self-refresh cycle is generated. So be sure to clear RPC2 to "0" (refresh disabled) before selecting the refresh method. EPSON B-II-4-26 S1C33L03 FUNCTION PART...
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Use RASC to choose the number of RAS cycles when accessing DRAM. Table 4.22 Number of RAS Cycles RASC1 RASC0 Number of cycles 4 cycles 3 cycles 2 cycles 1 cycle The initial default value is 1 cycle. EPSON S1C33L03 FUNCTION PART B-II-4-27...
BCLK COL #1 COL #2 A[11:0] #RASx #HCAS/ #LCAS data data D[15:0] Figure 4.31 DRAM Read Cycle (EDO page mode) The read timing in EDO page-mode lags 0.5 cycles behind that in fast page mode. EPSON B-II-4-28 S1C33L03 FUNCTION PART...
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Example: RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle; byte-write sample (little endian) Precharge RAS cycle CAS cycle #1 CAS cycle #2 cycle BCLK A[11:0] #RASx #HCAS #LCAS Undefined write data D[15:8] write data Undefined D[7:0] Figure 4.34 DRAM Byte-Write Cycle (fast page or EDO page mode) EPSON S1C33L03 FUNCTION PART B-II-4-29...
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• relinquishing of bus control is requested by an external bus master. Note: When using the successive RAS mode, always be sure to use #DRD for the read signal and #DWE for the low-byte write signal. EPSON B-II-4-30 S1C33L03 FUNCTION PART...
The refresh RAS pulse width is determined by the timing at which the refresh is deactivated in software and is unaffected by settings of RRA. #RAS and #HCAS/#LCAS are booted up simultaneously upon completion of a self-refresh and the precharge duration that follows is fixed at 6 cycles. EPSON S1C33L03 FUNCTION PART B-II-4-31...
#BUSREQ pin is released back high. Unlike in the case of ordinary releasing of the bus by #BUSREQ, the address bus and bus control signals are not placed in high-impedance state. For a DRAM refresh request that may arise in this HALT state, take one of the corrective measures described above. EPSON S1C33L03 FUNCTION PART B-II-4-33...
1 8 bits 0 16 bits A14DF1 Areas 14–13 A14DF[1:0] Number of cycles A14DF0 output disable delay time – reserved – – – 0 when being read. A14WT2 Areas 14–13 wait control A14WT[2:0] Wait cycles A14WT1 A14WT0 EPSON B-II-4-34 S1C33L03 FUNCTION PART...
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1 8 bits 0 16 bits A8DF1 Areas 8–7 A8DF[1:0] Number of cycles A8DF0 output disable delay time – reserved – – – 0 when being read. A8WT2 Areas 8–7 wait control A8WT[2:0] Wait cycles A8WT1 A8WT0 EPSON S1C33L03 FUNCTION PART B-II-4-35...
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A1X1MD Area 1 access-speed 1 2 cycles 0 4 cycles x2 speed mode only – reserved – – 0 when being read. BCLKSEL1 BCLK output clock selection BCLKSEL[1:0] BCLK BCLKSEL0 PLL_CLK OSC3_CLK BCU_CLK CPU_CLK EPSON S1C33L03 FUNCTION PART B-II-4-37...
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AxxWT. Wait cycles derived from the #WAIT pin also can be inserted in the cycle for writing to the burst ROM area. At cold start, these bits are set to "111" (7 cycles). At hot start, the bits retain their status before being initialized. EPSON B-II-4-38 S1C33L03 FUNCTION PART...
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ROM write cycle. For the burst ROM write cycle, the wait cycles set via the #WAIT pin can also be used. At cold start, A10BW is set to "0" (no wait cycle). At hot start, A10BW retains its status before being initialized. EPSON S1C33L03 FUNCTION PART...
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The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM. At cold start, REDO is set to "0" (fast-page mode). At hot start, REDO retains its status before being initialized. EPSON B-II-4-40...
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The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM. At cold start, RPC0 is set to "0" (1 cycle). At hot start, RPC0 retains its status before being initialized. EPSON S1C33L03 FUNCTION PART...
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CPU is placed in a HALT state, allowing for reduction in power consumption. At cold start, SEPD is set to "0" (disabled). At hot start, SEPD retains its status before being initialized. EPSON B-II-4-42 S1C33L03 FUNCTION PART...
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Furthermore, when CEFUNC is set to "10" or "11", four chip enable signal is expanded into two area size. At cold start, CEFUNC is set to "00". At hot start, CEFUNC retains its status before being initialized. EPSON S1C33L03 FUNCTION PART...
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The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM. At cold start, RASC is set to "0" (1 cycle). At hot start, RASC retains its status before being initialized. EPSON B-II-4-44...
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If AxxAS is set to "0", the signal output is disabled. At cold start, these bits are set to "0" (disabled). At hot start, these bits retain their status before being initialized. EPSON S1C33L03 FUNCTION PART...
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4. When the CPU stops by the HALT or SLP instruction, this clock is also stopped. This clock is almost in phase with the bus clock. At initial reset, BCLKSEL is set to "00" (CPU_CLK). EPSON B-II-4-46 S1C33L03 FUNCTION PART...
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When x1 speed mode is set (#X2SPD pin = "1"), area 1 is always accessed in 2 cycles regardless of the A1X1MD value. At cold start, A1X1MD is set to "0" (4 cycles). At hot start, A1X1MD retains its status before being initialized. EPSON S1C33L03 FUNCTION PART B-II-4-47...
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II CORE BLOCK: BCU (Bus Control Unit) THIS PAGE IS BLANK. EPSON B-II-4-48 S1C33L03 FUNCTION PART...
Edge (rising or falling) or level (High or Low) 46 70(Base+118) Port input interrupt 6 Edge (rising or falling) or level (High or Low) 47 71(Base+11C) Port input interrupt 7 Edge (rising or falling) or level (High or Low) EPSON S1C33L03 FUNCTION PART B-II-5-1...
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The PSR and interrupt control register will be detailed later. For details about interrupt factor generating conditions, refer to the description of each peripheral circuit in this manual. EPSON B-II-5-2 S1C33L03 FUNCTION PART...
If an interrupt to be generated upon completion of IDMA is disabled at the setting of the IDMA side, no interrupt request is signaled to the CPU. Therefore, the CPU remains idle until the next interrupt request is generated. EPSON S1C33L03 FUNCTION PART B-II-5-3...
However, since an occurrence of NMI or the like between writes of the low-order and high-order half-words would cause a malfunction, it is recommended that the register be written in words. EPSON B-II-5-4 S1C33L03 FUNCTION PART...
IL is rewritten. The IL is restored to its previous status when the interrupt processing routine is terminated by the reti instruction. EPSON S1C33L03 FUNCTION PART B-II-5-5...
For details about interrupt factor generating conditions, refer to the description of each peripheral circuit in this manual. EPSON B-II-5-6 S1C33L03 FUNCTION PART...
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These signals remain asserted until the interrupt factor flag is reset to "0" or the corresponding bit of the interrupt enable register is set to "0" (interrupts are disabled) or until some other interrupt factor of higher priority occurs. They are not cleared if the CPU simply accepts the interrupt request. EPSON S1C33L03 FUNCTION PART B-II-5-7...
However, if the interrupt level of the IL is set below the current level and the IE is set to enable interrupts before resetting the interrupt factor flag after an interrupt has occurred, the same interrupt may occur again. EPSON B-II-5-8 S1C33L03 FUNCTION PART...
An IDMA invocation request is accepted even when the interrupt enable register and PSR of the CPU is set to disable interrupts. It is also necessary that the control information for the IDMA channel has been set. EPSON S1C33L03 FUNCTION PART...
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Reset B signal (reset IDMA request bit) Reset C signal (reset IDMA enable bit) IDMA request bit "1" IDMA enable bit Figure 5.3 Sequence when DINTEN = "0" For details on IDMA, refer to "IDMA (Intelligent DMA)". EPSON B-II-5-10 S1C33L03 FUNCTION PART...
Before HSDMA can be invoked by the occurrence of an interrupt factor, it is necessary that DMA be enabled on the HSDMA side by setting the control register for HSDMA transfer. For details about HSDMA, refer to "HSDMA (High-Speed DMA)". EPSON S1C33L03 FUNCTION PART B-II-5-11...
0 when being read. interrupt P16T32 16-bit timer 3 interrupt level 0 to 7 priority register P16T31 P16T30 – reserved – – – 0 when being read. P16T22 16-bit timer 2 interrupt level 0 to 7 P16T21 P16T20 EPSON B-II-5-12 S1C33L03 FUNCTION PART...
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– reserved – – – 0 when being read. E16TC2 16-bit timer 2 comparison A 1 Enabled 0 Disabled E16TU2 16-bit timer 2 comparison B D1–0 – reserved – – – 0 when being read. EPSON S1C33L03 FUNCTION PART B-II-5-13...
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0 No factor is flag register FSRX1 SIF Ch.1 receive buffer full generated generated FSERR1 SIF Ch.1 receive error FSTX0 SIF Ch.0 transmit buffer empty FSRX0 SIF Ch.0 receive buffer full FSERR0 SIF Ch.0 receive error EPSON B-II-5-14 S1C33L03 FUNCTION PART...
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DEP4 Port input 4 register – reserved – – – 0 when being read. DEADE A/D converter 1 IDMA 0 IDMA DESTX1 SIF Ch.1 transmit buffer empty enabled disabled DESRX1 SIF Ch.1 receive buffer full EPSON S1C33L03 FUNCTION PART B-II-5-15...
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IDMA enable register set method 1 Set only 0 RD/WR register selection IDMAONLY IDMA request register set method 1 Set only 0 RD/WR selection RSTONLY Interrupt factor flag reset method 1 Reset only 0 RD/WR selection EPSON B-II-5-16 S1C33L03 FUNCTION PART...
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Fixed at 0 0 when being read. order register (HW) TTBR32 Writing 1 not allowed. TTBR31 TTBR30 TTBR2B Trap table base address [27:16] 0x0C0 TTBR2A TTBR29 TTBR28 TTBR27 TTBR26 TTBR25 TTBR24 TTBR23 TTBR22 TTBR21 TTBR20 EPSON S1C33L03 FUNCTION PART B-II-5-17...
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For the interrupt factors used to request IDMA invocation or clear the standby mode, the corresponding interrupt enable register bit must be set for interrupt enable. When initially reset, this register is set to "0" (interrupt disabled). EPSON B-II-5-18 S1C33L03 FUNCTION PART...
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DMA transfer, the IDMA request register is reset to "0" and an interrupt request for the interrupt factor that enabled IDMA invoking is generated. After an initial reset, this register is set to "0" (Interrupt is requested). EPSON S1C33L03 FUNCTION PART B-II-5-19...
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IDMA request bit can be reset by the hardware between the read and the write, so be careful when using this method. After an initial reset, IDMAONLY is set to "1" (set-only method). EPSON B-II-5-20 S1C33L03 FUNCTION PART...
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Write "1": SIO Ch.3 receive error Write "0": FP2 input Read: Valid Set to "1" to use the SIO Ch.3 receive error interrupt. Set to "0" to use the FP2 input interrupt. At power-on, this bit is set to "0". EPSON S1C33L03 FUNCTION PART B-II-5-21...
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Write "1": 8-bit timer 5 underflow Write "0": FP7 input Read: Valid Set to "1" to use the 8-bit timer 5 underflow interrupt. Set to "0" to use the FP7 input interrupt. At power-on, this bit is set to "0". EPSON B-II-5-22 S1C33L03 FUNCTION PART...
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Write "0": TM16 Ch.3 compare B Read: Valid Set to "1" to use the SIO Ch.2 receive error interrupt. Set to "0" to use the TM16 Ch.3 compare B interrupt. At power-on, this bit is set to "0". EPSON S1C33L03 FUNCTION PART B-II-5-23...
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Before writing to the TTBR register, set TBRP to "0x59" to remove the write protection. Then when data is written to the most significant byte (0x48137) of the TTBR, the register once again becomes write-protected. After an initial reset, TBRP is set to "0x0" (write protected). EPSON B-II-5-24 S1C33L03 FUNCTION PART...
(5) To prevent another interrupt from being generated for the same factor again after generation of an interrupt, be sure to reset the interrupt factor flag before enabling interrupts and setting the PSR again or executing the reti instruction. EPSON S1C33L03 FUNCTION PART B-II-5-25...
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II CORE BLOCK: ITC (Interrupt Controller) THIS PAGE IS BLANK. EPSON B-II-5-26 S1C33L03 FUNCTION PART...
CPU and turn off the high-speed (OSC3) oscillation circuit in order to reduce current consumption. In addition, when SLEEP mode is set, the high-speed (OSC3) oscillation circuit is turned off, greatly reducing current consumption (no internal units except for the clock timer need to be operated). EPSON S1C33L03 FUNCTION PART B-II-6-1...
Note: When using the PLL, the oscillation frequency range changes according to the PLL setting. See Table 6.2. For details on oscillation characteristics and the external clock input characteristics, refer to "Electrical Characteristics". EPSON B-II-6-2 S1C33L03 FUNCTION PART...
(for 3.3-V crystal resonator, this time is 10 ms max.). To prevent the device from operating erratically, do not use the clock until its oscillation has stabilized. The high-speed (OSC3) oscillation circuit turns off when the CPU is set in SLEEP mode. EPSON S1C33L03 FUNCTION PART B-II-6-3...
3. Switch over the CPU operating clock (by writing "1" to CLKCHG). Note: The operating clock switchover by CLKCHG is effective only when both oscillation circuits are on and the power-control register protection flag is set to "0b10010110". EPSON B-II-6-4 S1C33L03 FUNCTION PART...
Note: The function for waiting until the high-speed (OSC3) oscillation is stabilized by 8T1ON is effective only when SLEEP mode is exited. Writing to 8T1ON is effective only when the power-control register protection flag is set to "0b10010110". EPSON S1C33L03 FUNCTION PART B-II-6-5...
Writing to SOSC3 is allowed only when CLGP[7:0] is set to "0b10010110". Note also that if the CPU is operating using the OSC3 clock, writing "0" to SOSC3 is ignored and the oscillation is not turned off. At initial reset, SOSC3 is set to "1" (OSC3 oscillation turned on). EPSON B-II-6-6 S1C33L03 FUNCTION PART...
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Writing to HLT2OP is allowed only when CLGP[7:0] is set to "0b10010110". At initial reset, HLT2OP is set to "0" (basic mode). The following shows the operating status in HALT mode (basic mode and HALT2 mode) and SLEEP mode. EPSON S1C33L03 FUNCTION PART B-II-6-7...
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This clearing of write protection is effective for only one writing, so the bits are cleared to "0b00000000" by one writing. Therefore, CLGP[7:0] must be set each time the protected address is written to. At initial reset, CLGP is set to "0b00000000" (write-protected). EPSON B-II-6-8 S1C33L03 FUNCTION PART...
Therefore, a restart is effected when the input level from a port is active by level. Consequently, the system design should assume that a restart by means of port input from the SLEEP state or HALT2 state is performed by level. EPSON S1C33L03 FUNCTION PART B-II-6-9...
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If the peripheral circuit clock frequency is equal to or higher than the base clock frequency, the peripheral circuit does not operate normally. EPSON B-II-6-10 S1C33L03 FUNCTION PART...
S1C33 Family) can be connected to these pins. Leave these pins open if the S5U1C33000H is not connected. For connecting the S5U1C33000H, refer to the "S5U1C33000H Manual (S1C33 Family In-Circuit Debugger)". Furthermore, the pin status is fixed as shown in the above table after a user reset. EPSON S1C33L03 FUNCTION PART B-II-7-1...
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II CORE BLOCK: DBG (Debug Unit) THIS PAGE IS BLANK. EPSON B-II-7-2 S1C33L03 FUNCTION PART...
C33_ADC C33_PERI Pads Intro (A/D converter) (Prescaler, 8-bit timer, 16-bit timer, Clock timer, Serial interface, Ports) C33 Analog Block C33 Peripheral Block Figure 1.1 Peripheral Block Note: Internal ROM is not provided in the S1C33L03. EPSON S1C33L03 FUNCTION PART B-III-1-1...
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III PERIPHERAL BLOCK: INTRODUCTION THIS PAGE IS BLANK. EPSON B-III-1-2 S1C33L03 FUNCTION PART...
(DRAM refresh), A/D converter, serial interface, and ports) that use the prescaler input clock (the source clock for prescaler) can be turned off, stop the prescaler by writing "0" to PSCON. This helps to reduce current consumption. EPSON S1C33L03 FUNCTION PART B-III-2-1...
The clock output is controlled by the P8TONx bit even if P8TPCKx is set to "1". When P8TPCKx is "0", the divided clock that is selected by P8TSx[2:0] will be output to the 8-bit timer x. At initial reset, P8TPCKx is set to "0" and P8TSx[2:0] becomes effective. EPSON B-III-2-2 S1C33L03 FUNCTION PART...
P16TON2 16-bit timer 2 clock control 1 On 0 Off register P16TS22 16-bit timer 2 P16TS2[2:0] Division ratio : selected by P16TS21 clock division ratio selection /4096 Prescaler clock select P16TS20 /1024 register (0x40181) /256 EPSON S1C33L03 FUNCTION PART B-III-2-3...
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1 On 0 Off P8TS02 8-bit timer 0 P8TS0[2:0] Division ratio : selected by P8TS01 clock division ratio selection /256 Prescaler clock select P8TS00 /128 register (0x40181) 8-bit timer 0 can generate the DRAM refresh clock. EPSON B-III-2-4 S1C33L03 FUNCTION PART...
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(e.g., 16-bit programmable timers, 8-bit programmable timers, A/D converter, serial interface, and ports). Therefore, do not turn off the prescaler when these peripheral circuits are used. At initial reset, PSCON is set to "1" (On). EPSON S1C33L03 FUNCTION PART B-III-2-5...
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The desired division ratio can be selected from among the eight ratios shown on the I/O map. Note that the division ratio differs for each peripheral circuit. These bits can also be read out. At initial reset, all of these bits are set to "0b000" (highest frequency available). EPSON B-III-2-6 S1C33L03 FUNCTION PART...
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The clock output is controlled by the P8TONx bit even if P8TPCKx is set to "1". When "0" is written, the divided clock that is selected by P8TSx[2:0] will be output to the 8-bit timer x. At initial reset, P8TPCKx is set to "0" (divided clock). EPSON S1C33L03 FUNCTION PART B-III-2-7...
(B) stops. When some these circuits of the above (A) need to be used, turn off all other unnecessary circuits and stop the clock supply from the prescaler to those circuits. EPSON B-III-2-8...
8-bit programmable timer. At cold start, the register is set to input mode. At hot start, the register retains its status from prior to the reset. EPSON S1C33L03 FUNCTION PART...
CPU can be started up by that underflow signal. To use this function, write "0" to the oscillation circuit control bit 8T1ON (D2) / Clock option register (0x40190) to enable the oscillation stabilization waiting function. EPSON B-III-3-2 S1C33L03 FUNCTION PART...
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5 by dividing it by 2 is supplied to the serial interface as its operating clock. This enables the transfer rate of the serial interface to be programmed. To use this function, write "0" to the serial interface control bit SSCK3 (D2) / Serial I/F Ch.3 control register (0x401F8) to select the internal clock. EPSON S1C33L03 FUNCTION PART B-III-3-3...
"Prescaler".) • Do not use a clock that is faster than the CPU operating clock as the 8-bit programmable timer. • When setting an input clock, make sure the 8-bit programmable timer is turned off. EPSON B-III-3-4 S1C33L03 FUNCTION PART...
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When the terminal count is reached and the counter underflows, the initial value is reloaded from the reload data register into the counter. EPSON S1C33L03 FUNCTION PART B-III-3-5...
3) The timer output is left as "0" when the timer output is turned on after setting the input clock and timer initial value. 4) When an underflow occurs after starting the timer, the port outputs a pulse with the same width as the 8-bit timer input clock pulse (prescaler's output). EPSON S1C33L03 FUNCTION PART B-III-3-7...
The registers can also be set so as not to generate an interrupt, with only a DMA transfer performed. For details on IDMA transfers and interrupt control upon completion of IDMA transfer, refer to "IDMA (Intelligent DMA)". EPSON B-III-3-8 S1C33L03 FUNCTION PART...
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Timer 0 underflow interrupt: 0x0C000D0 Timer 1 underflow interrupt: 0x0C000D4 Timer 2 underflow interrupt: 0x0C000D8 Timer 3 underflow interrupt: 0x0C000DC The base address of the trap table can be changed using the TTBR register (0x48134 to 0x48137). B-III EPSON S1C33L03 FUNCTION PART B-III-3-9...
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I/F Ch.0 PSIO02 Serial interface Ch.0 0 to 7 interrupt PSIO01 interrupt level priority register PSIO00 – reserved – – – 0 when being read. P8TM2 8-bit timer 0–3 interrupt level 0 to 7 P8TM1 P8TM0 EPSON S1C33L03 FUNCTION PART B-III-3-11...
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0 P21, etc. CFEX1 P10, P11, P13 port extended 1 DST0 0 P10, etc. function DST1 P11, etc. DPC0 P13, etc. CFEX0 P12, P14 port extended function 1 DST2 0 P12, etc. DCLK P14, etc. EPSON B-III-3-12 S1C33L03 FUNCTION PART...
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There are two cases in which the reload data is loaded into the counter: when data is preset after "1" is written to PSETx, or when data is automatically reloaded upon counter underflow. At initial reset, RLD is not initialized. EPSON S1C33L03 FUNCTION PART B-III-3-13...
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While in a STOP state, the counter retains its count until it is preset with reload data or placed in a RUN state. When the state is changed from STOP to RUN, the counter can restart counting beginning with the retained count. At initial reset, PTRUNx is set to "0" (STOP). EPSON B-III-3-14 S1C33L03 FUNCTION PART...
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When written using the reset-only method (default) Write "1": Interrupt factor flag is reset Write "0": Invalid When written using the read/write method Write "1": Interrupt flag is set Write "0": Interrupt flag is reset EPSON S1C33L03 FUNCTION PART B-III-3-15...
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If the bit is set to "0", normal interrupt processing is performed and IDMA is not invoked. For details on IDMA, refer to "IDMA (Intelligent DMA)". At initial reset, R8TUx is set to "0" (interrupt request). EPSON B-III-3-16 S1C33L03 FUNCTION PART...
(6) To prevent another interrupt from being generated again by the same factor after an interrupt has occurred, be sure to reset the interrupt factor flag (F8TUx) before setting the PSR again or executing the reti instruction. EPSON S1C33L03 FUNCTION PART...
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III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS THIS PAGE IS BLANK. EPSON B-III-3-18 S1C33L03 FUNCTION PART...
When the counter value matches to the content of each comparison data register, the comparator outputs a signal that controls the interrupt and the output signal. Thus the registers allow interrupt generating intervals and the timer's output clock frequency and duty ratio to be programmed. EPSON S1C33L03 FUNCTION PART B-III-4-1...
Therefore, it is necessary to set the I/O port's I/O control bit IOC1x to "0" in advance. At cold start, these pins are set in input mode. At hot start, they retain their status from prior to the reset. EPSON B-III-4-2 S1C33L03 FUNCTION PART...
To use this function, write "1" to the watchdog timer control bit EWD (D1) / Watchdog timer enable register (0x40171) to enable the NMI. For details on how to control the watchdog timer, refer to "Watchdog Timer". 16TM EPSON S1C33L03 FUNCTION PART B-III-4-3...
Notes: • When the internal clock is used, the 16-bit programmable timer operates only when the prescaler is operating (refer to "Prescaler"). • When setting an input clock, make sure the 16-bit programmable timer is turned off. EPSON B-III-4-4 S1C33L03 FUNCTION PART...
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This comparison match signal controls the clock output (TMx signal) to external devices, in addition to generating an interrupt. The comparison data B is also used to reset the counter. EPSON S1C33L03 FUNCTION PART B-III-4-5...
1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 Comparison match A signal Comparison match B signal PTMx TMx output (when OUTINVx = "0") TMx output (when OUTINVx = "1") Figure 4.3 Waveform of 16-Bit Programmable Timer Output EPSON S1C33L03 FUNCTION PART B-III-4-7...
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A = 0 and B = 1. In this case, the timer output clock cycle is the input clock 1/2. 3) When the comparison data registers are set as A > B, no comparison A signal is generated. In this case, the output signal is fixed at the off level. EPSON B-III-4-8 S1C33L03 FUNCTION PART...
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Transfer conditions, etc. must also be set on the HSDMA side. If a 16-bit timer is selected as the HSDMA trigger, the HSDMA channel is invoked through generation of the interrupt factor. For details on HSDMA transfer, refer to "HSDMA (High-Speed DMA)". EPSON B-III-4-10 S1C33L03 FUNCTION PART...
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Serial interface Ch.2 and Ch.3 share interrupt signals with the 16-bit timers. A register setting determined which is used. The initial setting is for use of the 16-bit timers. Refer to Section III-8, "Serial Interface", for details of the settings. B-III 16TM EPSON S1C33L03 FUNCTION PART B-III-4-11...
0 when being read. F16TC4 16-bit timer 4 comparison A 1 Factor is 0 No factor is F16TU4 16-bit timer 4 comparison B generated generated D1–0 – reserved – – – 0 when being read. EPSON B-III-4-12 S1C33L03 FUNCTION PART...
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IOC14 P14 I/O control of the I/O control IOC13 P13 I/O control signals of the ports IOC12 P12 I/O control when it is read. (See IOC11 P11 I/O control detailed explanation.) IOC10 P10 I/O control EPSON S1C33L03 FUNCTION PART B-III-4-13...
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1 External clock 0 Internal clock PTM0 16-bit timer 0 clock output control 1 On 0 Off PRESET0 16-bit timer 0 reset 1 Reset 0 Invalid 0 when being read. PRUN0 16-bit timer 0 Run/Stop control 1 Run 0 Stop EPSON B-III-4-14 S1C33L03 FUNCTION PART...
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16-bit timer 2 comparison data A 0 to 65535 comparison (HW) CR2A14 CR2A15 = MSB data A set-up CR2A13 CR2A0 = LSB register CR2A12 CR2A11 CR2A10 CR2A9 CR2A8 CR2A7 CR2A6 CR2A5 CR2A4 CR2A3 CR2A2 CR2A1 CR2A0 EPSON S1C33L03 FUNCTION PART B-III-4-15...
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16-bit timer 3 comparison data B 0 to 65535 comparison (HW) CR3B14 CR3B15 = MSB data B set-up CR3B13 CR3B0 = LSB register CR3B12 CR3B11 CR3B10 CR3B9 CR3B8 CR3B7 CR3B6 CR3B5 CR3B4 CR3B3 CR3B2 CR3B1 CR3B0 EPSON B-III-4-16 S1C33L03 FUNCTION PART...
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00481A4 TC415 16-bit timer 4 counter data 0 to 65535 counter data (HW) TC414 TC415 = MSB register TC413 TC40 = LSB TC412 TC411 TC410 TC49 TC48 TC47 TC46 TC45 TC44 TC43 TC42 TC41 TC40 EPSON S1C33L03 FUNCTION PART B-III-4-17...
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1 External clock 0 Internal clock PTM5 16-bit timer 5 clock output control 1 On 0 Off PRESET5 16-bit timer 5 reset 1 Reset 0 Invalid 0 when being read. PRUN5 16-bit timer 5 Run/Stop control 1 Run 0 Stop EPSON B-III-4-18 S1C33L03 FUNCTION PART...
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IOC register. At cold start, IOC1x is set to "0" (input mode). At hot start, the bit retains its state from prior to the initial reset. EPSON S1C33L03 FUNCTION PART B-III-4-19...
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By writing "1" to OUTINVx, an active-low signal (off level = high) is generated for the TMx output. When OUTINVx is set to "0", an active-high signal (off level = low) is generated. At initial reset, OUTINVx is set to "0" (active high). EPSON B-III-4-20 S1C33L03 FUNCTION PART...
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Write "0": Invalid Read: Always "0" The counter of timer x is reset by writing "1" to PRESETx. Writing "0" results in No Operation. Since PRESETx is a write-only bit, its content when read is always "0". EPSON S1C33L03 FUNCTION PART B-III-4-21...
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The data set in this register is compared with each corresponding counter data. When the contents match, a comparison B interrupt is generated and the output signal falls (OUTINVx = "0") or rises (OUTINVx = "1"). Furthermore, the counter is reset to "0". At initial reset, CRxB is not initialized. EPSON B-III-4-22 S1C33L03 FUNCTION PART...
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When written using the reset-only method (default) Write "1": Interrupt factor flag is reset Write "0": Invalid When written using the read/write method Write "1": Interrupt flag is set Write "0": Interrupt flag is reset EPSON S1C33L03 FUNCTION PART B-III-4-23...
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When the register is set to "0", normal interrupt processing is performed and IDMA is not invoked. For details on IDMA, refer to "IDMA (Intelligent DMA)". At initial reset, these bits are set to "0" (interrupt request). EPSON B-III-4-24 S1C33L03 FUNCTION PART...
TMx signal falls with the comparison A signal, a high level pulse will be generated if "0" is written to PTMx before setting the port to low. It can be prevented by writing "0" to PTMx after setting the port to low. EPSON S1C33L03 FUNCTION PART B-III-4-25...
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III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS THIS PAGE IS BLANK. EPSON B-III-4-26 S1C33L03 FUNCTION PART...
For the 16-bit programmable timer 0, set an appropriate comparison B value to make it start operating. If the watchdog timer function is not to be used, set EWD to "0" and do not change it. EPSON S1C33L03 FUNCTION PART...
In SLEEP mode, the prescaler is turned off. Therefore, the watchdog timer also stops operating. To prevent generation of an unwanted NMI after clearing SLEEP mode, reset the 16-bit programmable timer 0 before executing the slp instruction. In addition, disable generation of the NMI by EWD as necessary. EPSON B-III-5-2 S1C33L03 FUNCTION PART...
(2) Even when EWD is set to "0", the 16-bit programmable timer 0 does not stop counting. Therefore, if the NMI has been temporarily disabled, be sure to reset the 16-bit programmable timer 0 before setting EWD back to "1". EPSON S1C33L03 FUNCTION PART B-III-5-3...
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III PERIPHERAL BLOCK: WATCHDOG TIMER THIS PAGE IS BLANK. EPSON B-III-5-4 S1C33L03 FUNCTION PART...
The oscillation frequency is 32.768 kHz (Typ.). Use a crystal resonator or external clock that oscillates at this frequency. No other frequency can be used for clock applications. For details on oscillation characteristics and the external clock input characteristics, refer to "Electrical Characteristics". EPSON B-III-6-2 S1C33L03 FUNCTION PART...
3. Switch over the CPU operating clock (by writing "1" to CLKCHG). Note: The operating clock switchover by CLKCHG is effective only when both oscillation circuits are on and the power-control register protection flag is set to "0b10010110". EPSON S1C33L03 FUNCTION PART B-III-6-3...
To start clock output, write "1" to PF1ON (D0) / Clock option register (0x40190). The clock output is stopped by writing "0". At initial reset, PF1ON is set to "0" (output disabled). PF1ON register FOSC1(P14) pin output Figure 6.3 OSC1 Clock Output EPSON B-III-6-4 S1C33L03 FUNCTION PART...
0 P21, etc. CFEX1 P10, P11, P13 port extended 1 DST0 0 P10, etc. function DST1 P11, etc. DPC0 P13, etc. CFEX0 P12, P14 port extended function 1 DST2 0 P12, etc. DCLK P14, etc. EPSON S1C33L03 FUNCTION PART B-III-6-5...
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When "1" is written to HLT2OP, the CPU will enter HALT2 mode when the HALT instruction is executed. When "0" is written, the CPU will enter basic mode. Writing to HLT2OP is allowed only when CLGP[7:0] is set to "0b10010110". At initial reset, HLT2OP is set to "0" (basic mode). EPSON B-III-6-6 S1C33L03 FUNCTION PART...
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This clearing of write protection is effective for only one writing, so the bits are cleared to "0b00000000" by one writing. Therefore, CLGP[7:0] must be set each time the protected address is written to. At initial reset, CLGP is set to "0b00000000" (write-protected). EPSON S1C33L03 FUNCTION PART B-III-6-7...
This helps reduce current consumption. (6) When the P14/FOSC1/DCLK pin is used as the FOSC1 output pin, set IOC14 (D4/0x402D6) to "1" (output) in addition to the CFP14 (D4/0x402D4) and CFEX0 (D0/0x402DF) settings. EPSON B-III-6-8 S1C33L03 FUNCTION PART...
B-III Interrupt/alarm Interrupt request Comparator Comparator Comparator select circuit (to interrupt controller) Alarm generation control circuit 6-bit minute 5-bit hour 5-bit day comparison comparison comparison data data data Figure 7.1 Structure of Clock Timer EPSON S1C33L03 FUNCTION PART B-III-7-1...
When using the clock timer as an RTC, be sure to set these counter values before starting operating of the clock timer. For the day counter, set a number of days starting from the reference day (e.g., January 1, 1990). EPSON B-III-7-2...
Page 333
0xFF and then overflows before reading the next seconds counter, the value of the seconds counter is its count plus the one second that has elapsed since the 8-bit binary counter was read. To prevent this problem, try reading out each counter several times and make sure data has not been modified. EPSON S1C33L03 FUNCTION PART B-III-7-3...
(D1) / Port input 4–7, clock timer, A/D interrupt factor flag register (0x40287) also is set to "1". At this time, if the interrupt conditions set by the interrupt control registers are met, an interrupt to the CPU is generated. EPSON B-III-7-4...
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Note that the clock timer interrupt factor does not have a function to invoke an intelligent DMA. Trap vectors The trap vector addresses for the clock-timer interrupt by default are set to 0x0C00104. The trap table base address can be changed using the TTBR registers (0x48134 to 0x48137). EPSON S1C33L03 FUNCTION PART B-III-7-5...
TCIF and alarm factor generation flag TCAF. If TCAF is set to 1, the interrupt has been caused by an alarm. If you select an interrupt factor (other than a 1-day factor) along with the hour-specified alarm, the selected interrupt factor occurs at the same time as the alarm factor. EPSON B-III-7-6 S1C33L03 FUNCTION PART...
TCND1 TCND0 Clock timer 0040158 TCND15 Clock timer day counter data 0 to 65535 days day (high- TCND14 (high-order 8 bits) (high-order 8 bits) order) register TCND13 TCND15 = MSB TCND12 TCND11 TCND10 TCND9 TCND8 EPSON S1C33L03 FUNCTION PART B-III-7-7...
Page 338
Writing "0" to TCRST results in No Operation. Since this TCRST is a write-only bit, its value when read is always "0". The clock timer is not reset by an initial reset. EPSON B-III-7-8 S1C33L03 FUNCTION PART...
Page 339
When the clock timer interrupt is enabled, an interrupt is generated cyclically at each falling edge of the selected signal. If you the interrupt caused by these factors is not be used set TCISE to "111". TCISE is not initialized at initial reset. EPSON S1C33L03 FUNCTION PART B-III-7-9...
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This bit does not affect generation of an alarm even if it is set to "1" or "0". PCTM2–PCTM0: Clock timer interrupt level (D[2:0]) / Clock timer interrupt priority register (0x4026B) Sets the priority level of the clock timer interrupt between 0 and 7. At initial reset, PCTM becomes indeterminate. EPSON B-III-7-10 S1C33L03 FUNCTION PART...
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Note also that the value to be written to reset the flag is "1" when the reset-only method (RSTONLY = "1") is used, and "0" when the read/write method (RSTONLY = "0") is used. The FCTM flag becomes indeterminate at initial reset, so be sure to reset it in the software. EPSON S1C33L03 FUNCTION PART B-III-7-11...
(7) To prevent regeneration of interrupts with the same factor after an interrupt has occurred, be sure to reset the interrupt factor flag (FCTM) before setting the PSR again or executing the reti instruction. EPSON B-III-7-12 S1C33L03 FUNCTION PART...
0, 1, 2, or 3 to indicate the channel number, enabling discrimination between channels 0 to 3. In this manual, however, channel numbers 0 to 3 are replaced with "x" unless discrimination is necessary, because explanations are common to all four channels. EPSON S1C33L03 FUNCTION PART B-III-8-1...
P0x (function select bit Pxx, CFPxx = "0"). When using the serial interface, make function select bit settings for the pins used, according to the channel and transfer mode to be used. At hot start, the pins retain their status from prior to the reset. EPSON B-III-8-2 S1C33L03 FUNCTION PART...
0x401E4, Ch.1: 0x401E9, Ch.2: 0x401F4, Ch.3: 0x401F9) is provided. Since these bits become indeterminate at initial reset, be sure to initialize them by writing "00" when using as the normal interface or "10" when using as the IrDA interface. EPSON S1C33L03 FUNCTION PART B-III-8-3...
Start bit: None Stop bit: None Parity bit: None #SCLKx Data D0 D1 D2 D3 D4 D5 D6 D7 Figure 8.3 Clock-Synchronized Transfer Data Format Serial data is transmitted and received starting with the LSB. EPSON B-III-8-4 S1C33L03 FUNCTION PART...
To ensure that the duty ratio of the clock to be fed to the serial interface is 50%, the 8-bit programmable timer further divides the underflow signal frequency by 2 internally. This 1/2 frequency division is factored into Eq. EPSON S1C33L03 FUNCTION PART...
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This mode operates using the clock that is output by the external master. This clock is input from the #SCLK pin. Therefore, there is no need to control the prescaler or 8-bit programmable timer. Initialize SSCKx by writing "1" (#SCLKx). EPSON B-III-8-6 S1C33L03 FUNCTION PART...
When data is transmitted successively in clock-synchronized master mode, TENDx maintains "1" until all data is transmitted (Figure 8.4). In slave mode, TENDx goes "0" every time 1-byte data is transmitted (Figure 8.5). Following explains transmit operation in both the master and slave modes. EPSON S1C33L03 FUNCTION PART B-III-8-7...
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At the same time, the LSB of the data transferred to the shift register is output from the SOUTx pin. The #SRDYx signal is returned to a high level at this point. EPSON B-III-8-8 S1C33L03 FUNCTION PART...
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Ch.2 receive data: RXD2[7:0] (D[7:0]) / Serial I/F Ch.2 receive data register (0x401F1) Ch.3 receive data: RXD3[7:0] (D[7:0]) / Serial I/F Ch.3 receive data register (0x401F6) The receive data can be read out from this register. EPSON S1C33L03 FUNCTION PART B-III-8-9...
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An overrun error occurs because the receive operation has completed when RDBFx = "1". 3rd data is read. Send the busy signal to the master device to stop the clock. Figure 8.7 Receive Timing Chart in Clock-Synchronized Slave Mode EPSON B-III-8-10 S1C33L03 FUNCTION PART...
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(5) Terminating receive operation Upon completion of a data receive operation, write "0" to the receive-enable bit RXENx to disable receive operations. EPSON S1C33L03 FUNCTION PART B-III-8-11...
(Stop bit: 2 bits, parity: non) (Stop bit: 2 bits, parity: used) s1: start bit, s2 & s3: stop bit, p: parity bit Figure 8.9 Data Format for Asynchronous Transfer Serial data is transmitted and received, starting with the LSB. EPSON B-III-8-12 S1C33L03 FUNCTION PART...
Therefore, before the internal clock can be used, the following conditions must be met: 1. The prescaler is outputting a clock to the 8-bit programmable timer 2 (or 3). 2. The 8-bit programmable timer 2 (or 3) is outputting a clock. EPSON S1C33L03 FUNCTION PART B-III-8-13...
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Any desired clock frequency can be set. The clock input from the #SCLKx pin is internally divided by 16 or 8 in the serial interface, in order to create a sampling clock (refer to "Sampling clock"). This division ratio must also be considered when setting the transfer rate. EPSON B-III-8-14 S1C33L03 FUNCTION PART...
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Figure 8.11 Sampling Clock for Asynchronous Transmit Operation (when 1/16 division is selected) When transmitting data, a sampling clock of a 50% duty cycle is generated from TCLK by dividing it by 16 (or 8), and each bit of data is output synchronously with this clock. EPSON S1C33L03 FUNCTION PART B-III-8-15...
This bit is reset to "0" by writing data to the transmit data register, and set back to "1" (buffer empty) when the data is transferred to the shift register. The transfer begins when the serial interface starts sending the start bit. EPSON B-III-8-16 S1C33L03 FUNCTION PART...
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For details on how to control interrupts and IDMA requests, refer to "Serial Interface Interrupts and DMA". (3) Terminating transmit operations When data transmission is completed, write "0" to the transmit-enable bit TXENx to disable transmit operations. EPSON S1C33L03 FUNCTION PART B-III-8-17...
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4. When the stop bit is sampled, the data in the shift register is transferred to the receive data register, enabling the data to be read out. The parity is checked when data is transferred to the receive data register (if EPRx = "1"). EPSON B-III-8-18 S1C33L03 FUNCTION PART...
Page 361
However, the content of the received data for which a framing error is flagged cannot be guaranteed, even if no framing error is found in the following data received. The FERx flag is reset to "0" by writing "0". EPSON S1C33L03 FUNCTION PART B-III-8-19...
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The OERx flag is reset to "0" by writing "0". (4) Terminating receive operation When a data receive operation is completed, write "0" to the receive-enable bit RXENx to disable receive operations. EPSON B-III-8-20 S1C33L03 FUNCTION PART...
RXENx are both set to "0"), as a change in settings during operation could cause a malfunction. In addition, be sure to set the transfer mode in (3) and the following items before selecting the IrDA interface function in (2). EPSON S1C33L03 FUNCTION PART B-III-8-21...
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PPM modulator input (SINx) PPM modulator output (I/F input) Figure 8.15 IRRLx and IRTLx Settings Note: The IRRLx and IRTLx bits become indeterminate at initial reset, so be sure to initialize them in the software. EPSON B-III-8-22 S1C33L03 FUNCTION PART...
PPM modulator output (I/F input) B-III 16 TCLK Figure 8.17 Demodulation by PPM Circuit Note: When using the IrDA interface, set the internal division ratio of the serial interface 1/16 (DIVMDx = "1"), rather than 1/8 (DIVMDx = "0"). EPSON S1C33L03 FUNCTION PART B-III-8-23...
Interrupts caused by an interrupt factor can be disabled by leaving the interrupt enable register bit for that factor set to "0". The interrupt factor flag is set to "1" whenever interrupt conditions are met, regardless of the setting of the interrupt enable register (even if it is set to "0"). EPSON B-III-8-24 S1C33L03 FUNCTION PART...
Page 367
IDMA side must also be set in advance. Table 8.11 Control Bits for IDMA Transfer Channel Interrupt factor IDMA request bit IDMA enable bit Ch.0 Receive-buffer full RSRX0(D6/0x40292) DESRX0(D6/0x40296) Transmit-buffer empty RSTX0(D7/0x40292) DESTX0(D7/0x40296) Ch.1 Receive-buffer full RSRX1(D0/0x40293) DESRX1(D0/0x40297) Transmit-buffer empty RSTX1(D1/0x40293) DESTX1(D1/0x40297) EPSON S1C33L03 FUNCTION PART B-III-8-25...
Page 368
"1011". Transfer conditions, etc. must also be set on the HSDMA side. The HSDMA channel is invoked through generation of the interrupt factor. For details on HSDMA transfer, refer to "HSDMA (High-Speed DMA)". EPSON B-III-8-26 S1C33L03 FUNCTION PART...
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Ch.2 and Ch.3 do not have dedicated interrupt signals. Either a port input interrupt or 16-bit timer interrupt is selected, and interrupt handling is performed accordingly. For details, refer to the "Trap Vector" subsection in the "16-Bit Programmable Timers" or "Input/Output Ports" section. EPSON S1C33L03 FUNCTION PART B-III-8-27...
RXD17 Serial I/F Ch.1 receive data 0x0 to 0xFF(0x7F) 7-bit asynchronous receive data RXD16 RXD17(16) = MSB mode does not use register RXD15 RXD10 = LSB RXD17 (fixed at 0). RXD14 RXD13 RXD12 RXD11 RXD10 EPSON B-III-8-28 S1C33L03 FUNCTION PART...
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1 Inverted 0 Direct Valid only in IRRL2 Ch.2 IrDA I/F input logic inversion 1 Inverted 0 Direct asynchronous mode. IRMD21 Ch.2 interface mode selection IRMD2[1:0] I/F mode IRMD20 reserved IrDA 1.0 reserved General I/F EPSON S1C33L03 FUNCTION PART B-III-8-29...
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0 TM16 Ch.4 RXD Full comp.B SIO2TS1 SIO Ch.2 transmit buffer empty 1 SIO Ch.2 0 TM16 Ch.5 TXD Emp. comp.A SIO2RS1 SIO Ch.2 receive buffer full 1 SIO Ch.2 0 TM16 Ch.5 RXD Full comp.B EPSON S1C33L03 FUNCTION PART B-III-8-31...
Page 374
To use the pin as SIN3, set SSIN3 (D0 / 0x402D7) to "1" and CFP33 (D3 / 0x402DC) to "0". To use the pin as P33 or #DMAACK1, set this bit to "0". At power-on, this bit is set to "0". EPSON B-III-8-32 S1C33L03 FUNCTION PART...
Page 375
To use the pin as SOUT2, set SSOUT2 (D1 / 0x402DB) to "1" and CFP26 (D6 / 0x402D8) to "0". To use the pin as P26 or TM4, set this bit to "0". At power-on, this bit is set to "0". EPSON S1C33L03 FUNCTION PART B-III-8-33...
Page 376
The serial-converted data is output from the SOUT pin beginning with the LSB, in which the bits set to "1" are output as high-level signals and those set to "0" output as low-level signals. This register can be read as well as written. At initial reset, the content of TXDx becomes indeterminate. EPSON B-III-8-34 S1C33L03 FUNCTION PART...
Page 377
"1". A framing error occurs when data with a stop bit = "0" is received in the asynchronous mode. The FERx flag is reset by writing "0". At initial reset, as well as when RXENx and TXENx both are set to "0", the FERx flag is set to "0" (no error). EPSON S1C33L03 FUNCTION PART B-III-8-35...
Page 378
TDBEx is set to "0" when transmit data is written to the transmit data register, and is set to "1" when this data is transferred to the shift register (transmit operation started). Transmit data is written to the transmit data register when this bit = "1". At initial reset, TDBEx is set to "1" (buffer empty). EPSON B-III-8-36 S1C33L03 FUNCTION PART...
Page 379
When RXENx for a channel is set to "1", the channel is enabled for receive operations. When RXENx is set to "0", the channel is disabled for receive operations. Always make sure the RXENx = "0" before setting the transfer mode and other conditions. At initial reset, RXENx is set to "0" (receive disabled). EPSON S1C33L03 FUNCTION PART B-III-8-37...
Page 380
STPBx is only valid in an asynchronous transfer. Two stop bits are selected by writing "1" to STPBx , and one stop bit is selected by writing "0". The start bit is fixed at 1 bit. Settings of STPBx are ignored during the performance of a clock-synchronized transfer. At initial reset, STPBx becomes indeterminate. EPSON B-III-8-38 S1C33L03 FUNCTION PART...
Page 381
"1", the sampling clock is generated from the input clock of the serial interface (output by an 8-bit programmable timer or input from #SCLKx) by dividing it by 8. When DIVMDx is set to "0", the input clock is divided by 16. At initial reset, DIVMDx becomes indeterminate. EPSON S1C33L03 FUNCTION PART B-III-8-39...
Page 382
Ch.1 interrupt level (D[2:0]) / Serial I/F Ch.1, A/D interrupt priority register (0x4026A) Sets the priority level of the serial-interface interrupt. The interrupt priority level can be set for each channel in the range of 0 to 7. At initial reset, PSIOx becomes indeterminate. EPSON B-III-8-40 S1C33L03 FUNCTION PART...
Page 383
Note also that the value to be written to reset the flag is "1" when the reset-only method (RSTONLY = "1") is used, and "0" when the read/write method (RSTONLY = "0") is used. At initial reset, all of these flags become indeterminate, so be sure to reset them in the software. EPSON S1C33L03 FUNCTION PART B-III-8-41...
Page 384
Write "1": SIO Ch.2 receive error Write "0": FP0 input Read: Valid Set to "1" to use the SIO Ch.2 receive error interrupt. Set to "0" to use the FP0 input interrupt. At power-on, this bit is set to "0". EPSON B-III-8-42 S1C33L03 FUNCTION PART...
Page 385
Write "1": 8-bit timer 4 underflow Write "0": FP5 input Read: Valid Set to "1" to use the 8-bit timer 4 underflow interrupt. Set to "0" to use the FP5 input interrupt. At power-on, this bit is set to "0". EPSON S1C33L03 FUNCTION PART B-III-8-43...
Page 386
Write "0": TM16 Ch.4 compare B Read: Valid Set to "1" to use the SIO Ch.3 receive-buffer full interrupt. Set to "0" to use the TM16 Ch.4 compare B interrupt. At power-on, this bit is set to "0". EPSON B-III-8-44 S1C33L03 FUNCTION PART...
Page 387
Write "0": TM16 Ch.2 compare A Read: Valid Set to "1" to use the 8-bit timer 5 underflow interrupt. Set to "0" to use the TM16 Ch.2 compare A interrupt. At power-on, this bit is set to "0". EPSON S1C33L03 FUNCTION PART B-III-8-45...
(11) When performing data transfer in the clock-synchronized mode, the division ratio of the prescaler and the reload data for the 8-bit programmable timer should be set so that the baud-rate is 1/4 of the system clock frequency or lower. (12) The serial interface operates only when the prescaler is operating. EPSON B-III-8-46 S1C33L03 FUNCTION PART...
Therefore, if these ports are not used, when the input level is fixed externally, it should be fixed at V or AV The K50 port is provided with a pull-up resistance that pulls the port up to AV EPSON S1C33L03 FUNCTION PART B-III-9-1...
V power supply to the AV power supply. 3) To fix the input level externally when the port is not used, the input pin should be connected to V or AV EPSON B-III-9-2 S1C33L03 FUNCTION PART...
(V ) respectively. Since this register is a read-only register, writing to the register is ignored. When the ports set for A/D converter input are read, the value obtained is always "0". EPSON S1C33L03 FUNCTION PART B-III-9-3...
#DMAEND1/ / #DMAEND1 output (O) / Serial IF Ch.3 data SOUT3 output (I): Input mode, (O): Output mode, (Ex): Extended function : A 3-V system I/O voltage can only be used for the P10–P14 pins. EPSON B-III-9-4 S1C33L03 FUNCTION PART...
At hot start, the pins retain their state from prior to the reset. Note: If pins P10–P14, P15–P16, P30 and P34 are set for use with peripheral circuits, their pin functions vary depending on the input/output direction control by the IOC1x register. EPSON S1C33L03 FUNCTION PART B-III-9-5...
IOC14 P14 I/O control of the I/O control IOC13 P13 I/O control signals of the ports IOC12 P12 I/O control when it is read. (See IOC11 P11 I/O control detailed explanation.) IOC10 P10 I/O control EPSON B-III-9-6 S1C33L03 FUNCTION PART...
Page 395
P34 I/O control indicates the values IOC33 P33 I/O control of the I/O control IOC32 P32 I/O control signals of the ports IOC31 P31 I/O control when it is read. (See IOC30 P30 I/O control detailed explanation.) EPSON S1C33L03 FUNCTION PART B-III-9-7...
Page 396
"1" is read out as input data; if the pin voltage is low (V level), "0" is read out as input data. At cold start, all data bits are set to "0". At hot start, they retain their state from prior to the initial reset. EPSON B-III-9-8 S1C33L03 FUNCTION PART...
Page 397
To use the pin as #SCLK3, set SSCLK3 (D2 / 0x402D7) to "1" and CFP15 (D5 / 0x402D4) to "0". To use the pin as P15, EXCL4, or #DMAEND0, set this bit to "0". At power-on, this bit is set to "0". EPSON S1C33L03 FUNCTION PART B-III-9-9...
Page 398
To use the pin as #SRDY2, set SSRDY2 (D3 / 0x402DB) to "1" and CFP24 (D4 / 0x402D8) to "0". To use the pin as P24 or TM2, set this bit to "0". At power-on, this bit is set to "0". EPSON B-III-9-10 S1C33L03 FUNCTION PART...
Page 399
At cold start, CFEX0 and CFEX1 are set to "1" (function-extended pin) and other bits are set to "0" (I/O- port/peripheral-circuit pin). At hot start, CFEX retains its state from prior to the initial reset. B-III EPSON S1C33L03 FUNCTION PART B-III-9-11...
Page 401
When the input signal goes to the selected status, the interrupt factor flag FP is set to "1" and, if other interrupt conditions set by the interrupt controller are met, an interrupt is generated. B-III EPSON S1C33L03 FUNCTION PART B-III-9-13...
Page 403
K50, interrupt will be generated when non- conformity occurs between the contents of the four bits K51–K54 and the four bits input comparison register SCPK0[4:1]. Figure 9.5 FPK0 Interrupt Generation Example (when K5[4:0] is selected by SPPK[1:0]) EPSON S1C33L03 FUNCTION PART B-III-9-15...
For IDMA to be invoked, the IDMA request and IDMA enable bits shown in Table 9.9 must be set to "1" in advance. Transfer conditions, etc. must also be set on the IDMA side in advance. EPSON B-III-9-16 S1C33L03 FUNCTION PART...
Page 405
0x0C00054 FPT4 input interrupt: 0x0C00110 FPT5 input interrupt: 0x0C00114 B-III FPT6 input interrupt: 0x0C00118 FPT7 input interrupt: 0x0C0011C The base address of the trap table can be changed using the TTBR register (0x48134 to 0x48137). EPSON S1C33L03 FUNCTION PART B-III-9-17...
0 when being read. port input 0–3 Key input 1 1 Factor is 0 No factor is interrupt factor Key input 0 generated generated flag register Port input 3 Port input 2 Port input 1 Port input 0 EPSON B-III-9-18 S1C33L03 FUNCTION PART...
Page 408
Table 9.11 Selecting Pins for Port Input Interrupts Interrupt SPT settings system FPT7 FPT6 FPT5 FPT4 FPT3 FPT2 FPT1 FPT0 At cold start, SPT is set to "00". At hot start, SPT retains its state from prior to the initial reset. EPSON B-III-9-20 S1C33L03 FUNCTION PART...
Page 409
(except for the inputs disabled from interrupt by the SMPK register). At cold start, SCPK is set to "0" (rising edge). At hot start, SCPK retains its state from prior to the initial reset. EPSON S1C33L03 FUNCTION PART B-III-9-21...
Page 410
EP and EK are interrupt enable bits corresponding to the port-input interrupt and the key-input interrupt, respectively. Interrupts for input systems set to "1" are enabled, and interrupts for input systems set to "0" are disabled. At initial reset, these bits are set to "0" (interrupt disabled). EPSON B-III-9-22 S1C33L03 FUNCTION PART...
Page 411
Note also that the value to be written to reset the flag is "1" when the reset-only method (RSTONLY = "1") is used, and "0" when the read/write method (RSTONLY = "0") is used. At initial reset, all the flags become indeterminate, so be sure to reset them in the software. EPSON S1C33L03 FUNCTION PART B-III-9-23...
Page 412
If DEP is set to "1", the IDMA request by the interrupt factor is enabled. If the register bit is set to "0", the IDMA request is disabled. After an initial reset, DEP is set to "0" (IDMA disabled). EPSON B-III-9-24 S1C33L03 FUNCTION PART...
Therefore, a restart is effected when the input level from a port is active by level. Consequently, the system design should assume that a restart by means of port input from the SLEEP state or HALT2 state is performed by level. B-III EPSON S1C33L03 FUNCTION PART B-III-9-25...
Page 414
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS THIS PAGE IS BLANK. EPSON B-III-9-26 S1C33L03 FUNCTION PART...
C33_PERI Pads (A/D converter) (Prescaler, 8-bit timer, 16-bit timer, Clock timer, Serial interface, Ports) C33 Analog Block C33 Peripheral Block Figure 1.1 Analog Block Note: Internal ROM is not provided in the S1C33L03. B-IV Intro EPSON S1C33L03 FUNCTION PART B-IV-1-1...
Page 418
IV ANALOG BLOCK: INTRODUCTION THIS PAGE IS BLANK. EPSON B-IV-1-2 S1C33L03 FUNCTION PART...
Successive Analog Analog Data approximation input block register block decoder Control circuit #ADTRG Interrupt 8-bit timer 0 control circuit 16-bit timer 0 B-IV Clock Interrupt request Prescaler generator Figure 2.1 Structure of A/D Converter EPSON S1C33L03 FUNCTION PART B-IV-2-1...
At cold start, the #ADTRG and AD[7:0] pins all are set for input ports Kxx (function select bit CFKxx = "0"). When using these pins for the A/D converter, write "1" to the function select bit CFKxx. At hot start, these pins retain their state from prior to the reset. EPSON B-IV-2-2 S1C33L03 FUNCTION PART...
To enable A/D conversions in multiple channels to be performed successively through one convert operation, specify the conversion start and conversion end channels. Conversion start channel: CS[2:0] (D[2:0]) / A/D channel register (0x40243) Conversion end channel: CE[2:0] (D[5:3]) / A/D channel register (0x40243) EPSON S1C33L03 FUNCTION PART B-IV-2-3...
Page 422
For details on how to set a timer, refer to the explanation of each programmable timer in this manual. 3. Software trigger Writing "1" to ADST (D1) / A/D enable register (0x40244) in the software serves as a trigger to start A/D conversion. EPSON B-IV-2-4 S1C33L03 FUNCTION PART...
When a trigger is input while ADE = "1", A/D conversion is started. If a software trigger has been selected, A/D conversion is started by writing "1" to ADST (D1) / A/D enable register (0x40244). Only the trigger selected using TS[1:0] (D[4:3]) / A/D trigger register (0x40242) are valid; no other trigger is accepted. EPSON S1C33L03 FUNCTION PART B-IV-2-5...
Page 424
Note that writing "0" to ADE cannot terminate the A/D conversion under-way (ADST = "1"). Note: Once A/D conversion ends, further A/D conversion will not be performed correctly if restarted within an interval shorter than one cycle of the A/D converter operating clock set by the prescaler. EPSON B-IV-2-6 S1C33L03 FUNCTION PART...
HSDMA side. If the A/D interrupt factor is selected as the HSDMA trigger, the HSDMA channel is invoked through generation of the interrupt factor. For details on HSDMA transfer, refer to "HSDMA (High-Speed DMA)". EPSON S1C33L03 FUNCTION PART B-IV-2-7...
Page 426
IV ANALOG BLOCK: A/D CONVERTER Trap vector The A/D converter's interrupt trap-vector default address is set to 0x0C00100. The base address of the trap table can be changed using the TTBR register (0x48134 to 0x48137). EPSON B-IV-2-8 S1C33L03 FUNCTION PART...
Reset by writing 0. A/D sampling 0040245 D7–2 – – – – – 0 when being read. register Input signal sampling time setup ST[1:0] Sampring time Use with 9 clocks. 9 clocks 7 clocks 5 clocks 3 clocks EPSON S1C33L03 FUNCTION PART B-IV-2-9...
Page 428
If the function select bit for a pin is set to "0", the pin is set for an input port. At cold start, CFK is set to "0" (input port). At hot start, CFK retains its state from prior to the initial reset. EPSON B-IV-2-10...
Page 429
Analog inputs can be A/D-converted successively from the channel set using this bit to the channel set using CE in one operation. If only one channel is to be A/D converted, set the same channel number in both the CS and CE bits. At initial reset, CS is set to "0" (AD0). EPSON S1C33L03 FUNCTION PART B-IV-2-11...
Page 430
OWE is not set. Once OWE is set to "1", it remains set until it is reset by writing "0" in the software. At initial reset, OWE is set to "0" (normal). EPSON B-IV-2-12 S1C33L03 FUNCTION PART...
Page 431
CPU is generated for the interrupt factor that has occurred. If interrupts are enabled at the setting of IDMA, an interrupt is generated under the above conditions after the data transfer by IDMA is completed. EPSON S1C33L03 FUNCTION PART B-IV-2-13...
Page 432
If DEADE is set to "1", the IDMA request by the interrupt factor is enabled. If this bit is set to "0", the IDMA request is disabled. After an initial reset, DEADE is set to "0" (IDMA disabled). EPSON B-IV-2-14 S1C33L03 FUNCTION PART...
ADD[9:0] is overwritten when the same conversion results have already been read (when ADF is reset to B-IV "0"). This may occur when the program reads the same results twice or more for verification or other purposes. EPSON S1C33L03 FUNCTION PART B-IV-2-15...
Page 434
IV ANALOG BLOCK: A/D CONVERTER THIS PAGE IS BLANK. EPSON B-IV-2-16 S1C33L03 FUNCTION PART...
C33_ADC C33_PERI Pads (A/D converter) (Prescaler, 8-bit timer, 16-bit timer, Clock timer, Serial interface, Ports) C33 Analog Block C33 Peripheral Block Figure 1.1 DMA Block Note: Internal ROM is not provided in the S1C33L03. Intro EPSON S1C33L03 FUNCTION PART B-V-1-1...
Page 438
V DMA BLOCK: INTRODUCTION THIS PAGE IS BLANK. EPSON B-V-1-2 S1C33L03 FUNCTION PART...
In this manual, however, channel numbers 0 to 3 are designated with an "x" except where they must be distinguished, as the explanation is the same for all channels. • The single-address transfer method does not allow data transfer to/from the SDRAM. EPSON S1C33L03 FUNCTION PART B-V-2-1...
If this pin is directed for input, it functions as a 16-bit programmable timer's event counter input and cannot be used to output the #DMAENDx signal. At cold start, this pin is set for input. At hot start, it retains the previous status. EPSON B-V-2-2 S1C33L03 FUNCTION PART...
Page 443
The address is incremented by an amount equal to the data size set by DATSIZEx when one data transfer is completed. The address that has been incremented during transfer does not return to the initial value. HSDMA EPSON S1C33L03 FUNCTION PART B-V-2-5...
Note that the control information cannot be set when HSx_EN = "1". When HSx_EN is set to "0", HSDMA requests are no longer accepted. When a DMA transfer is completed (transfer counter = 0), HSx_EN is reset to "0" to disable the following trigger inputs. HSDMA EPSON S1C33L03 FUNCTION PART B-V-2-7...
By writing "1" to this bit, the set trigger flag can be cleared if the DMA transfer has not been started. When this bit is read, "1" indicates that the flag is set and "0" indicates that the flag is cleared. EPSON B-V-2-8...
(3) The addresses are incremented or decremented according to the SxIN/DxIN settings. (4) The transfer counter is decremented. (5) The HSDMA enable bit HSx_EN is cleared and HSDMA interrupt factor flag in ITC is set when the transfer counter reaches 0 (when DINTENx = "1"). EPSON S1C33L03 FUNCTION PART B-V-2-9...
Page 448
(5) Steps (1) to (4) are repeated until the transfer counter reaches 0. (6) The HSDMA enable bit HSx_EN is cleared and HSDMA interrupt factor flag in ITC is set when the transfer counter reaches 0 (when DINTENx = "1"). EPSON B-V-2-10 S1C33L03 FUNCTION PART...
Page 449
(5) If SxIN or DxIN is "10", the address is recycled to the initial value. (6) The transfer counter is decremented. (7) The HSDMA enable bit HSx_EN is cleared and HSDMA interrupt factor flag in ITC is set when the transfer counter reaches 0 (when DINTENx = "1"). EPSON S1C33L03 FUNCTION PART B-V-2-11...
When the transfer counter reaches 0, the end-of-transfer signal is output from the #DMAENDx pin indicating that a specified number of transfers has been completed. At the same time, the interrupt factor for the completion of HSDMA is generated. EPSON B-V-2-12 S1C33L03 FUNCTION PART...
Example: Page mode, RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle Read cycle Write cycle BCLK COL #1 COL #2 COL #1 COL #2 A[11:0] #RASx #HCAS/ #LCAS #DMAEND Figure 2.7 #DMAEND Signal Output Timing (DRAM) HSDMA EPSON S1C33L03 FUNCTION PART B-V-2-13...
Page 452
Example: Page mode, RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle BCLK COL #1 COL #2 A[11:0] #RASx #HCAS/ #LCAS #DMAACK #DMAEND Figure 2.10 #DMAACK/#DMAEND Signal Output Timing (DRAM) Note: The single-address transfer method does not allow data transfer to/from the SDRAM. EPSON B-V-2-14 S1C33L03 FUNCTION PART...
CPU actually accepts a HSDMA interrupt. For details about the interrupt control register and for the device operation when an interrupt occurs, refer to "ITC (Interrupt Controller)". HSDMA EPSON S1C33L03 FUNCTION PART B-V-2-15...
Page 454
Channel 0 end-of-transfer interrupt: 0x0C00058 Channel 1 end-of-transfer interrupt: 0x0C0005C Channel 2 end-of-transfer interrupt: 0x0C00060 Channel 3 end-of-transfer interrupt: 0x0C00064 Note that the trap table base address can be modified using the TTBR registers (0x48134 to 0x48137). EPSON B-V-2-16 S1C33L03 FUNCTION PART...
Page 465
If CFP1x is set to "0", the pin is set for an I/O port. At cold start, CFP1x is set to "0" (I/O port). At hot start, CFP1x retains the previous status before an initial reset. EPSON S1C33L03 FUNCTION PART...
Page 466
When CFEXx is set to "0", the corresponding CFP bit becomes effective. At cold start, these bits are set to "0" (I/O-port/serial interface I/O pin). At hot start, these bits retain the previous status before an initial reset. EPSON B-V-2-28 S1C33L03 FUNCTION PART...
Page 467
By reading HSx_TF, the flag status can be checked. Writing "1" to HSx_TF clears the trigger flag if the DMA transfer has not been started. At initial reset, HSx_TF is set to "0". EPSON S1C33L03 FUNCTION PART B-V-2-29...
Page 468
Data transfer from an external I/O device to external memory is performed by writing "1" to DxDIR. Data transfer from external memory to an external I/O is performed by writing "0". At initial reset, DxDIR is set to "0" (memory to I/O). This bit is effective only in single-address mode. EPSON B-V-2-30 S1C33L03 FUNCTION PART...
Page 469
However, if SxIN is set to "10", the source address that has been incremented during a block transfer recycles back to the initial value when the block transfer is completed. At initial reset, SxIN is set to "00" (Fixed). EPSON S1C33L03 FUNCTION PART B-V-2-31...
Page 470
Even when the counter is 0, a DMA request is accepted and the counter is decremented to "0xFFFF" (or "0xFFFFFF"). Be sure to disable DMA transfers (HSx_EN = "0") before writing and re