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Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual

Cmos 32-bit single chip microcomputer
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Table of Contents
MF1574 - 01
CMOS 32 - BIT SINGLE CHIP MICROCOMPUTER
S1C33L03
Technical Manual
S1C33L03 PRODUCT PART
S1C33L03 FUNCTION PART

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  Summary of Contents for Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03

  • Page 1 MF1574 - 01 CMOS 32 - BIT SINGLE CHIP MICROCOMPUTER S1C33L03 Technical Manual S1C33L03 PRODUCT PART S1C33L03 FUNCTION PART...
  • Page 2 No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any...
  • Page 3 S1C33L03 Technical Manual This manual describes the hardware specifications of the Seiko Epson original 32-bit microcomputer S1C33L03. S1C33L03 PRODUCT PART Describes the hardware specifications of the S1C33L03 except for details of the peripheral circuits. S1C33L03 FUNCTION PART Describes details of all the peripheral circuit blocks for the S1C33 Family microcomputers.

  • Page 5: Table Of Contents

    8.6.5 LCD Interface AC Characteristics ................A-96 8.7 Oscillation Characteristics....................A-107 8.8 PLL Characteristics ......................A-108 9 Package ..........................A-109 9.1 Plastic Package ........................A-109 10 Pad Layout .........................A-110 10.1 Pad Layout Diagram......................A-110 10.2 Pad Coordinate........................A-111 EPSON S1C33L03 TECHNICAL MANUAL...
  • Page 6 Appendix A <Reference> External Device Interface Timings.......... A-113 A.1 DRAM (70ns)........................A-114 A.2 DRAM (60ns)........................A-117 A.3 ROM and Burst ROM ......................A-121 A.4 SRAM (55ns) ........................A-123 A.5 SRAM (70ns) ........................A-125 A.6 8255A............................ A-127 Appendix B Pin Characteristics ................... A-128 EPSON S1C33L03 TECHNICAL MANUAL...
  • Page 7 Setting Device Type and Size ..................B-II-4-10 Setting SRAM Timing Conditions................. B-II-4-11 Setting Timing Conditions of Burst ROM ..............B-II-4-12 Bus Operation........................... B-II-4-13 Data Arrangement in Memory ..................B-II-4-13 Bus Operation of External Memory ................B-II-4-13 EPSON S1C33L03 TECHNICAL MANUAL...
  • Page 8 Power-Control Register Protection Flag ..................B-II-6-5 Operation in Standby Mode ....................... B-II-6-5 I/O Memory of Clock Generator ....................B-II-6-6 Programming Notes........................B-II-6-9 II-7 DBG (Debug Unit)......................B-II-7-1 Debug Circuit ..........................B-II-7-1 I/O Pins of Debug Circuit......................B-II-7-1 EPSON S1C33L03 TECHNICAL MANUAL...
  • Page 9 Switching Over the CPU Operating Clock ................B-III-6-3 Power-Control Register Protection Flag ................... B-III-6-4 Operation in Standby Mode ......................B-III-6-4 OSC1 Clock Output to External Devices .................. B-III-6-4 I/O Memory of Low-Speed (OSC1) Oscillation Circuit ............. B-III-6-5 Programming Notes........................B-III-6-8 EPSON S1C33L03 TECHNICAL MANUAL...
  • Page 10 I/O Control Register and I/O Modes................B-III-9-5 I/O Memory of I/O Ports....................B-III-9-6 Input Interrupt .......................... B-III-9-12 Port Input Interrupt....................... B-III-9-12 Key Input Interrupt ....................... B-III-9-14 Control Registers of the Interrupt Controller............... B-III-9-16 I/O Memory for Input Interrupts ................... B-III-9-18 Programming Notes.........................B-III-9-25 EPSON S1C33L03 TECHNICAL MANUAL...
  • Page 11 I/O Memory of HSDMA......................B-V-2-17 Programming Notes........................B-V-2-36 V-3 IDMA (Intelligent DMA)....................B-V-3-1 Functional Outline of IDMA ......................B-V-3-1 Programming Control Information....................B-V-3-1 IDMA Invocation .........................B-V-3-5 Operation of IDMA........................B-V-3-8 Linking............................B-V-3-12 Interrupt Function of Intelligent DMA ..................B-V-3-13 I/O Memory of Intelligent DMA....................B-V-3-14 Programming Notes........................B-V-3-17 EPSON S1C33L03 TECHNICAL MANUAL...
  • Page 12 Look-up Tables ......................B-VII-2-11 Frame Rates ......................B-VII-2-19 Other Settings ......................B-VII-2-20 Display Control ........................B-VII-2-21 Controlling LCD Power Up/Down................B-VII-2-21 Reading/Writing Display Data ................... B-VII-2-22 Setting the Display Start Address ................B-VII-2-22 Split-Screen Display ....................B-VII-2-23 EPSON viii S1C33L03 TECHNICAL MANUAL...
  • Page 13 Portrait Mode ......................B-VII-2-25 Power Save........................ B-VII-2-29 Controlling the GPIO Pins ..................B-VII-2-30 I/O Memory of LCD Controller....................B-VII-2-31 Programming Notes....................... B-VII-2-42 Precautions on Using ICD33....................B-VII-2-42 Examples of LCD Controller Setting Program..............B-VII-2-43 APPENDIX I/O MAP EPSON S1C33L03 TECHNICAL MANUAL...

  • Page 15: S1C33L03 Product Part

    S1C33L03 PRODUCT PART...

  • Page 17: Outline

    1 OUTLINE 1 Outline The S1C33L03 is a Seiko Epson original 32-bit microcomputer with a built-in LCD controller. It features high speed, low power and low-voltage operation and is most suitable for portable equipment that needs display function, such as information terminals, E-mail terminals, electronic dictionaries.
  • Page 18 Note: The values of power consumption during execution were measured when a test program that consisted of 55% load instructions, 23% arithmetic operation instructions, 1% mac instruction, 12% branch instructions and 9% ext instruction was being continuously executed. Supply form QFP20-144pin plastic package, or chip. EPSON S1C33L03 PRODUCT PART...

  • Page 19: Block Diagram

    FPDAT[7:4] High-speed #DMAACKx(P32, P33, P04, P06) FPDAT[3:0]/GPO[6:3] DMA (4 ch.) #DMAENDx(P15, P16, P05, P07) FPFRAME LCD Controller FPLINE FPSHIFT DRDY(MOD/FPSHIFT2) LCDPWR P00–07 P10–16 K50–54 I/O Port Input Port P20–27 K60–67 P30–35 Figure 1.2.1 S1C33L03 Block Diagram EPSON S1C33L03 PRODUCT PART...

  • Page 20: Pin Description

    N.C. A12/SDA11 #CE3 K67/AD7 #CE8/#RAS1/#CE14/#RAS3/#SDCE1 A13/SDA12 K66/AD6 #CE7/#RAS0/#CE13/#RAS2/#SDCE0 A14/SDBA0 #CE10EX/#CE9&10EX K65/AD5 A15/SDBA1 #CE6/#CE7&8 K64/AD4 OSC2 #CE4/#CE11/#CE11&12 K63/AD3 OSC1 #X2SPD K62/AD2 #RESET P03/#SRDY0 K61/AD1 P35/#BUSACK/GPIO1 P02/#SCLK0 K60/AD0 P34/#BUSREQ/#CE6/GPIO0 P01/SOUT0 P33/#DMAACK1/SIN3/SDA10 P00/SIN0 Figure 1.3.1 Pin Layout Diagram (QFP20-144pin) EPSON S1C33L03 PRODUCT PART...

  • Page 21: Pin Functions

    Area 11 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "01" #CE11&12 * When CEFUNC[1:0] = "1x", this pin outputs #CE11+#CE12 signal. #CE3 – Area 3 chip enable – Read signal #EMEMRD – Read signal for internal ROM emulation memory EPSON S1C33L03 PRODUCT PART...
  • Page 22 Area read signal output for GA when CFEX3(D3/0x402DF) = "1" GPIO2: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and BREQEN(D2/0x39FFFD) = "0" EA10MD1 Pull-up Area 10 boot mode selection EA10MD1 EA10MD0 Mode EA10MD0 – External ROM mode Internal ROM mode EPSON S1C33L03 PRODUCT PART...
  • Page 23 I/O port when CFP07(D7/0x402D0) = "0" and CFEX7(D7/0x402DF) = "0" #SRDY1 (default) #DMAEND3 #SRDY1: Serial I/F Ch. 1 ready signal output when CFP07(D7/0x402D0) = "1" and CFEX5(D5/0x402DF) = "0" #DMAEND3: HSDMA Ch. 3 end-of-transfer signal output when CFEX7(D7/0x402DF) = "1" EPSON S1C33L03 PRODUCT PART...
  • Page 24 16-bit timer 0 event counter input when CFP10(D0/0x402D4) = "1", T8UF0 IOC10(D0/0x402D6) = "0" and CFEX1(D1/0x402DF) = "0" DST0 T8UF0: 8-bit timer 0 output when CFP10(D0/0x402D4) = "1", IOC10(D0/0x402D6) = "1" and CFEX1(D1/0x402DF) = "0" DST0: DST0 signal output when CFEX1(D1/0x402DF) = "1" (default) EPSON S1C33L03 PRODUCT PART...
  • Page 25 CFP24(D4/0x402D8) = "0" – P25: I/O port when CFP25(D5/0x402D8) = "0" (default) TM3: 16-bit timer 3 output when CFP25(D5/0x402D8) = "1" #SCLK2 #SCLK2: Serial I/F Ch. 2 clock input/output when SSCLK2(D2/0x402DB) = "1" and CFP25(D5/0x402D8) = "0" EPSON S1C33L03 PRODUCT PART...
  • Page 26 – P35: I/O port when CFP35(D5/0x402DC) = "0" (default) #BUSACK #BUSACK: Bus acknowledge output when CFP35(D5/0x402DC) = "1" and GPIO1 CFP34(D4/0x402DC) = "1" GPIO1: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and BREQEN(D2/0x39FFFD) = "0" EPSON A-10 S1C33L03 PRODUCT PART...
  • Page 27 1: CPU clock = bus clock 1, 0: CPU clock = bus clock #NMI Pull-up NMI request input pin #RESET Pull-up Initial reset input pin Note: "#" in the pin names indicates that the signal is low active. EPSON S1C33L03 PRODUCT PART A-11...

  • Page 28: Power Supply

    10 V pins. Be sure to supply the operating voltage to all the pins. Do not open any of them. The operating clock frequency range (OSC3) is 5 MHz to 50 MHz with this voltage. EPSON A-12 S1C33L03 PRODUCT PART...

  • Page 29: Power Supply For Analog Circuits (Av Dde

    Noise on the analog power lines decrease the A/D converting precision, so use a stabilized power supply and make the board pattern with consideration given to that. EPSON S1C33L03 PRODUCT PART A-13...

  • Page 30: Internal Memory

    The S1C33L03 does not have a built-in ROM. The boot address is fixed at 0x0C00000, and so external ROM/Flash should be used in Area 10. For setting up Area 10, refer to the "BCU (Bus Control Unit)" in "S1C33L03 FUNCTION PART" in this manual. EPSON A-14 S1C33L03 PRODUCT PART...

  • Page 31: Ram

    The S1C33L03 has a built-in 8KB RAM. The RAM is allocated to Area 0, address 0x0000000 to address 0x0001FFF. The internal RAM is a 32-bit sized device and data can be read/written in 1 cycle regardless of data size (byte, half- word or word). EPSON S1C33L03 PRODUCT PART A-15...

  • Page 32: Peripheral Circuits

    2, 4, 16 or 256-level (1, 2, 4 or 8 bit-per-pixel) color display Resolution examples: 640 480 pixels with 1bpp color depth 640 240 pixels with 2bpp color depth 320 240 pixels with 4bpp color depth 240 160 pixels with 8bpp color depth EPSON A-16 S1C33L03 PRODUCT PART...

  • Page 33: I/O Memory Map

    0, 1: Initial values that are set at initial reset. (However, the registers for the bus and input/output ports are not initialized at hot start.) Not initialized at initial reset. –: Not set in the circuit. EPSON S1C33L03 PRODUCT PART A-17...
  • Page 34 1 On 0 Off P8TS02 8-bit timer 0 P8TS0[2:0] Division ratio : selected by P8TS01 clock division ratio selection /256 Prescaler clock select P8TS00 /128 register (0x40181) 8-bit timer 0 can generate the DRAM refresh clock. EPSON A-18 S1C33L03 PRODUCT PART...
  • Page 35 Clock timer 0040154 D7–6 – reserved – – – 0 when being read. second TCMD5 Clock timer second counter data 0 to 59 seconds register TCMD4 TCMD5 = MSB TCMD3 TCMD0 = LSB TCMD2 TCMD1 TCMD0 EPSON S1C33L03 PRODUCT PART A-19...
  • Page 36 D7–5 – reserved – – – 0 when being read. TCCN4 Clock timer day comparison data 0 to 31 days Compared with comparison TCCN3 TCCN4 = MSB TCND[4:0]. register TCCN2 TCCN0 = LSB TCCN1 TCCN0 EPSON A-20 S1C33L03 PRODUCT PART...
  • Page 37 RLD20 = LSB RLD24 RLD23 RLD22 RLD21 RLD20 8-bit timer 2 004016A PTD27 8-bit timer 2 counter data 0 to 255 counter data PTD26 PTD27 = MSB register PTD25 PTD20 = LSB PTD24 PTD23 PTD22 PTD21 PTD20 EPSON S1C33L03 PRODUCT PART A-21...
  • Page 38 RLD50 = LSB RLD54 RLD53 RLD52 RLD51 RLD50 8-bit timer 5 004017A PTD57 8-bit timer 5 counter data 0 to 255 counter data PTD56 PTD57 = MSB register PTD55 PTD50 = LSB PTD54 PTD53 PTD52 PTD51 PTD50 EPSON A-22 S1C33L03 PRODUCT PART...
  • Page 39 Watchdog 0040171 D7–2 – – – – – 0 when being read. timer enable Watchdog timer enable 1 NMI enabled 0 NMI disabled register – – – – – 0 when being read. EPSON S1C33L03 PRODUCT PART A-23...
  • Page 40 Writing 10010110 (0x96) protect register CLGP6 removes the write protection of CLGP5 the power control register CLGP4 (0x40180) and the clock option CLGP3 register (0x40190). CLGP2 Writing another value set the CLGP1 write protection. CLGP0 EPSON A-24 S1C33L03 PRODUCT PART...
  • Page 41 1 Inverted 0 Direct Valid only in IRRL0 Ch.0 IrDA I/F input logic inversion 1 Inverted 0 Direct asynchronous mode. IRMD01 Ch.0 interface mode selection IRMD0[1:0] I/F mode IRMD00 reserved IrDA 1.0 reserved General I/F EPSON S1C33L03 PRODUCT PART A-25...
  • Page 42 OER2 Ch.2 overrun error flag 1 Error 0 Normal Reset by writing 0. TDBE2 Ch.2 transmit data buffer empty 1 Empty 0 Buffer full RDBF2 Ch.2 receive data buffer full 1 Buffer full 0 Empty EPSON A-26 S1C33L03 PRODUCT PART...
  • Page 43 1 Inverted 0 Direct Valid only in IRRL3 Ch.3 IrDA I/F input logic inversion 1 Inverted 0 Direct asynchronous mode. IRMD31 Ch.3 interface mode selection IRMD3[1:0] I/F mode IRMD30 reserved IrDA 1.0 reserved General I/F EPSON S1C33L03 PRODUCT PART A-27...
  • Page 44 Reset by writing 0. A/D sampling 0040245 D7–2 – – – – – 0 when being read. register Input signal sampling time setup ST[1:0] Sampring time Use with 9 clocks. 9 clocks 7 clocks 5 clocks 3 clocks EPSON A-28 S1C33L03 PRODUCT PART...
  • Page 45 0 when being read. interrupt P16T52 16-bit timer 5 interrupt level 0 to 7 priority register P16T51 P16T50 – reserved – – – 0 when being read. P16T42 16-bit timer 4 interrupt level 0 to 7 P16T41 P16T40 EPSON S1C33L03 PRODUCT PART A-29...
  • Page 46 0 when being read. interrupt PP7L2 Port input 7 interrupt level 0 to 7 priority register PP7L1 PP7L0 – reserved – – – 0 when being read. PP6L2 Port input 6 interrupt level 0 to 7 PP6L1 PP6L0 EPSON A-30 S1C33L03 PRODUCT PART...
  • Page 47 – – – 0 when being read. clock timer, Port input 7 1 Enabled 0 Disabled A/D interrupt Port input 6 enable register Port input 5 Port input 4 ECTM Clock timer EADE A/D converter EPSON S1C33L03 PRODUCT PART A-31...
  • Page 48 0 when being read. clock timer, A/D Port input 7 1 Factor is 0 No factor is interrupt factor Port input 6 generated generated flag register Port input 5 Port input 4 FCTM Clock timer FADE A/D converter EPSON A-32 S1C33L03 PRODUCT PART...
  • Page 49 DEP4 Port input 4 register – reserved – – – 0 when being read. DEADE A/D converter 1 IDMA 0 IDMA DESTX1 SIF Ch.1 transmit buffer empty enabled disabled DESRX1 SIF Ch.1 receive buffer full EPSON S1C33L03 PRODUCT PART A-33...
  • Page 50 IDMA enable register set method 1 Set only 0 RD/WR register selection IDMAONLY IDMA request register set method 1 Set only 0 RD/WR selection RSTONLY Interrupt factor flag reset method 1 Reset only 0 RD/WR selection EPSON A-34 S1C33L03 PRODUCT PART...
  • Page 51 K65 input port data – K64D K64 input port data – K63D K63 input port data – K62D K62 input port data – K61D K61 input port data – K60D K60 input port data – EPSON S1C33L03 PRODUCT PART A-35...
  • Page 52 0 TM16 Ch.4 RXD Full comp.B SIO2TS1 SIO Ch.2 transmit buffer empty 1 SIO Ch.2 0 TM16 Ch.5 TXD Emp. comp.A SIO2RS1 SIO Ch.2 receive buffer full 1 SIO Ch.2 0 TM16 Ch.5 RXD Full comp.B EPSON A-36 S1C33L03 PRODUCT PART...
  • Page 53 P16 I/O port data 1 High 0 Low P15D P15 I/O port data P14D P14 I/O port data P13D P13 I/O port data P12D P12 I/O port data P11D P11 I/O port data P10D P10 I/O port data EPSON S1C33L03 PRODUCT PART A-37...
  • Page 54 P34 I/O control indicates the values IOC33 P33 I/O control of the I/O control IOC32 P32 I/O control signals of the ports IOC31 P31 I/O control when it is read. (See IOC30 P30 I/O control detailed explanation.) EPSON A-38 S1C33L03 PRODUCT PART...
  • Page 55 1 8 bits 0 16 bits A14DF1 Areas 14–13 A14DF[1:0] Number of cycles A14DF0 output disable delay time – reserved – – – 0 when being read. A14WT2 Areas 14–13 wait control A14WT[2:0] Wait cycles A14WT1 A14WT0 EPSON S1C33L03 PRODUCT PART A-39...
  • Page 56 1 8 bits 0 16 bits A8DF1 Areas 8–7 A8DF[1:0] Number of cycles A8DF0 output disable delay time – reserved – – – 0 when being read. A8WT2 Areas 8–7 wait control A8WT[2:0] Wait cycles A8WT1 A8WT0 EPSON A-40 S1C33L03 PRODUCT PART...
  • Page 57 Writing 1 not allowed. SBUSST External interface method selection 1 #BSL 0 A0 SEMAS External bus master setup 1 Existing 0 Nonexistent SEPD External power-down control 1 Enabled 0 Disabled SWAITE #WAIT enable 1 Enabled 0 Disabled EPSON S1C33L03 PRODUCT PART A-41...
  • Page 58 Fixed at 0 0 when being read. order register (HW) TTBR32 Writing 1 not allowed. TTBR31 TTBR30 TTBR2B Trap table base address [27:16] 0x0C0 TTBR2A TTBR29 TTBR28 TTBR27 TTBR26 TTBR25 TTBR24 TTBR23 TTBR22 TTBR21 TTBR20 EPSON A-42 S1C33L03 PRODUCT PART...
  • Page 59 A1X1MD Area 1 access-speed 1 2 cycles 0 4 cycles x2 speed mode only – reserved – – 0 when being read. BCLKSEL1 BCLK output clock selection BCLKSEL[1:0] BCLK BCLKSEL0 PLL_CLK OSC3_CLK BCU_CLK CPU_CLK EPSON S1C33L03 PRODUCT PART A-43...
  • Page 60 1 External clock 0 Internal clock PTM0 16-bit timer 0 clock output control 1 On 0 Off PRESET0 16-bit timer 0 reset 1 Reset 0 Invalid 0 when being read. PRUN0 16-bit timer 0 Run/Stop control 1 Run 0 Stop EPSON A-44 S1C33L03 PRODUCT PART...
  • Page 61 1 External clock 0 Internal clock PTM1 16-bit timer 1 clock output control 1 On 0 Off PRESET1 16-bit timer 1 reset 1 Reset 0 Invalid 0 when being read. PRUN1 16-bit timer 1 Run/Stop control 1 Run 0 Stop EPSON S1C33L03 PRODUCT PART A-45...
  • Page 62 1 External clock 0 Internal clock PTM2 16-bit timer 2 clock output control 1 On 0 Off PRESET2 16-bit timer 2 reset 1 Reset 0 Invalid 0 when being read. PRUN2 16-bit timer 2 Run/Stop control 1 Run 0 Stop EPSON A-46 S1C33L03 PRODUCT PART...
  • Page 63 1 External clock 0 Internal clock PTM3 16-bit timer 3 clock output control 1 On 0 Off PRESET3 16-bit timer 3 reset 1 Reset 0 Invalid 0 when being read. PRUN3 16-bit timer 3 Run/Stop control 1 Run 0 Stop EPSON S1C33L03 PRODUCT PART A-47...
  • Page 64 1 External clock 0 Internal clock PTM4 16-bit timer 4 clock output control 1 On 0 Off PRESET4 16-bit timer 4 reset 1 Reset 0 Invalid 0 when being read. PRUN4 16-bit timer 4 Run/Stop control 1 Run 0 Stop EPSON A-48 S1C33L03 PRODUCT PART...
  • Page 65 1 External clock 0 Internal clock PTM5 16-bit timer 5 clock output control 1 On 0 Off PRESET5 16-bit timer 5 reset 1 Reset 0 Invalid 0 when being read. PRUN5 16-bit timer 5 Run/Stop control 1 Run 0 Stop EPSON S1C33L03 PRODUCT PART A-49...
  • Page 66 0048204 DSTART IDMA start 1 IDMA start 0 Stop register D6–0 DCHN IDMA channel number 0 to 127 IDMA enable 0048205 D7–1 – reserved – – – register IDMAEN IDMA enable 1 Enabled 0 Disabled EPSON A-50 S1C33L03 PRODUCT PART...
  • Page 67 Inc.(init) Dec.(no init) Note: Fixed D) Dual address S0ADRH11 D) Ch.0 source address[27:16] mode S0ADRH10 S) Ch.0 memory address[27:16] S) Single S0ADRH9 address S0ADRH8 mode S0ADRH7 S0ADRH6 S0ADRH5 S0ADRH4 S0ADRH3 S0ADRH2 S0ADRH1 S0ADRH0 EPSON S1C33L03 PRODUCT PART A-51...
  • Page 68 DF–1 – reserved – – – Undefined in read. DMA Ch.0 (HW) trigger flag HS0_TF Ch.0 trigger flag clear (writing) 1 Clear 0 No operation register Ch.0 trigger flag status (reading) 1 Set 0 Cleared EPSON A-52 S1C33L03 PRODUCT PART...
  • Page 69 Inc.(init) Dec.(no init) Note: Fixed D) Dual address S1ADRH11 D) Ch.1 source address[27:16] mode S1ADRH10 S) Ch.1 memory address[27:16] S) Single S1ADRH9 address S1ADRH8 mode S1ADRH7 S1ADRH6 S1ADRH5 S1ADRH4 S1ADRH3 S1ADRH2 S1ADRH1 S1ADRH0 EPSON S1C33L03 PRODUCT PART A-53...
  • Page 70 DF–1 – reserved – – – Undefined in read. DMA Ch.1 (HW) trigger flag HS1_TF Ch.1 trigger flag clear (writing) 1 Clear 0 No operation register Ch.1 trigger flag status (reading) 1 Set 0 Cleared EPSON A-54 S1C33L03 PRODUCT PART...
  • Page 71 Inc.(init) Dec.(no init) Note: Fixed D) Dual address S2ADRH11 D) Ch.2 source address[27:16] mode S2ADRH10 S) Ch.2 memory address[27:16] S) Single S2ADRH9 address S2ADRH8 mode S2ADRH7 S2ADRH6 S2ADRH5 S2ADRH4 S2ADRH3 S2ADRH2 S2ADRH1 S2ADRH0 EPSON S1C33L03 PRODUCT PART A-55...
  • Page 72 DF–1 – reserved – – – Undefined in read. DMA Ch.2 (HW) trigger flag HS2_TF Ch.2 trigger flag clear (writing) 1 Clear 0 No operation register Ch.2 trigger flag status (reading) 1 Set 0 Cleared EPSON A-56 S1C33L03 PRODUCT PART...
  • Page 73 Inc.(init) Dec.(no init) Note: Fixed D) Dual address S3ADRH11 D) Ch.3 source address[27:16] mode S3ADRH10 S) Ch.3 memory address[27:16] S) Single S3ADRH9 address S3ADRH8 mode S3ADRH7 S3ADRH6 S3ADRH5 S3ADRH4 S3ADRH3 S3ADRH2 S3ADRH1 S3ADRH0 EPSON S1C33L03 PRODUCT PART A-57...
  • Page 74 DF–1 – reserved – – – Undefined in read. DMA Ch.3 (HW) trigger flag HS3_TF Ch.3 trigger flag clear (writing) 1 Clear 0 No operation register Ch.3 trigger flag status (reading) 1 Set 0 Cleared EPSON A-58 S1C33L03 PRODUCT PART...
  • Page 75 SDRTRAS2 SDRAM t spec SDRTRAS[2:0] Number of clocks timing set-up SDRTRAS1 register 1 SDRTRAS0 D4–3 SDRTRP1 SDRAM t spec SDRTRP[1:0] Number of clocks SDRTRP0 D2–0 SDRTRC2 SDRAM t spec SDRTRC[2:0] Number of clocks SDRTRC1 SDRTRC0 EPSON S1C33L03 PRODUCT PART A-59...
  • Page 76 039FFCA SDRMRS SDRAM mode register set flag 1 Not finished 0 Done status register SDRSRM SDRAM current refresh mode 1 Auto refresh 0 Self refresh D5–0 – reserved – – – 0 when being read. EPSON A-60 S1C33L03 PRODUCT PART...
  • Page 77 V resolution (lines) - 1 register 1 LDVSIZE8 (high-order 2 bits) Horizontal 039FFE7 D7–5 – reserved – – – 0 when being read. non-display HNDP4 Horizontal non-display period Non-display period (pixels) period register HNDP3 HNDP2 HNDP1 HNDP0 EPSON S1C33L03 PRODUCT PART A-61...
  • Page 78 Memory address offset address offset MADOFS6 register MADOFS5 MADOFS4 MADOFS3 MADOFS2 MADOFS1 MADOFS0 Screen 1 039FFF2 S1VSIZE7 Screen 1 vertical size vertical size S1VSIZE6 (low-order 8 bits) register 0 S1VSIZE5 S1VSIZE4 S1VSIZE3 S1VSIZE2 S1VSIZE1 S1VSIZE0 EPSON A-62 S1C33L03 PRODUCT PART...
  • Page 79 P: 1/8, M: 1/4 P: 1/4, M: 1/2 P: 1/2, M: 1/1 P: 1/2, M: 1/1 Line byte 039FFFC PMODLBC7 Line byte count count register PMODLBC6 for portrait PMODLBC5 mode PMODLBC4 PMODLBC3 PMODLBC2 PMODLBC1 PMODLBC0 EPSON S1C33L03 PRODUCT PART A-63...
  • Page 80 (number of wait cycles for SRAM) VRAMWT0 EDMAEN External DMA enable 1 Enabled 0 Disabled BREQEN External bus-request enable 1 Enabled 0 Disabled LCDCST A0/BSL select 1 BSL 0 A0 LCDCEC Big/little endian select 1 Big endian 0 Little endian EPSON A-64 S1C33L03 PRODUCT PART...

  • Page 81: Power-Down Control

    Even during operation using the high-speed (OSC3) oscillation clock, power reduction can also be achieved through the use of a system clock derived from the OSC3 clock by dividing it (1/1, 1/2, 1/4, or 1/8). EPSON S1C33L03 PRODUCT PART A-65...
  • Page 82 8-bit timer 5 clock control P8TON5(D7)/8-bit timer 4/5 clock control register(0x40145) 8-bit timer 5 Run/Stop PTRUN5(D0)/8-bit timer 5 control register(0x40178) STOP STOP A/D converter clock control PSONAD(D3)/A/D clock control register(0x4014F) A/D conversion enable ADE(D2)/A/D enable register(0x40244) STOP STOP EPSON A-66 S1C33L03 PRODUCT PART...
  • Page 83 This may cause damage of the LCD panel if the clock supply to the LCD controller is stopped at the same time. Therefore, do not stop the clock supply for 1 frame cycles or more after setting the LCD controller to power save mode. EPSON S1C33L03 PRODUCT PART A-67...

  • Page 84: Basic External Wiring Diagram

    33 MHz (Max.) Gate capacitor 10 pF Drain capacitor 10 pF Feedback resistor Resistor 4.7 k Capacitor 100 pF Capacitor 5 pF Note: The above table is simply an example, and is not guaranteed to work. EPSON A-68 S1C33L03 PRODUCT PART...

  • Page 85: Precautions On Mounting

    • Sudden power supply variation due to noise may cause malfunction. Consider the following points to prevent this: (1) The power supply should be connected to the V and AV pins with patterns as short and large as possible. In particular, the power supply for AV affects A/D conversion precision. EPSON S1C33205 PRODUCT PART A-69...
  • Page 86 Do not arrange a high-speed signal line especially near circuits that are sensitive to noise such as the oscillation unit and analog input unit. Prohibited pattern K60 (AD0) OSC4 OSC3 Large current signal line High-speed signal line Large current signal line High-speed signal line EPSON A-70 S1C33205 PRODUCT PART...

  • Page 87: Electrical Characteristics

    High-level output current 1 pin Total of all pins Low-level output current 1 pin Total of all pins Analog power voltage -0.3 to +7.0 Analog input voltage -0.3 to AV +0.3 Storage temperature -65 to +150 °C EPSON S1C33L03 PRODUCT PART A-71...

  • Page 88: Recommended Operating Conditions

    – 32.768 – OSC1 Operating temperature °C Input rise time (normal input) – – Input fall time (normal input) – – Input rise time (schmitt input) – – Input fall time (schmitt input) – – EPSON A-72 S1C33L03 PRODUCT PART...

  • Page 89: Dc Characteristics

    Other than DSIO DSIO Pull-down resistor (ICEMD) Input pin capacitance – – f=1MHz, V Output pin capacitance – – f=1MHz, V I/O pin capacitance – – f=1MHz, V Note: See Appendix B for pin characteristics. EPSON S1C33L03 PRODUCT PART A-73...
  • Page 90 Other than DSIO DSIO Pull-down resistor (ICEMD) Input pin capacitance – – f=1MHz, V Output pin capacitance – – f=1MHz, V I/O pin capacitance – – f=1MHz, V Note: See Appendix B for pin characteristics. EPSON A-74 S1C33L03 PRODUCT PART...

  • Page 91: Current Consumption

    1: The values of current consumption while the CPU is operating were measured when a test program that consists of 55% load instructions, 23% arithmetic operation instructions, 1% mac instruction, 12% branch instructions and 9% ext instruction is being executed in the built-in ROM continuously. 2: The LCD controller is included. EPSON S1C33L03 PRODUCT PART A-75...

  • Page 92: A/D Converter Characteristics

    V[000]h = Ideal voltage at zero-scale point (=0.5LSB) 1LSB = V'[000]h = Actual voltage at zero-scale point V[3FF]h = Ideal voltage at full-scale point (=1022.5LSB) V'[3FF]h - V'[000]h 1LSB' = V'[3FF]h = Actual voltage at full-scale point EPSON A-76 S1C33L03 PRODUCT PART...
  • Page 93 [LSB] 1LSB' Actual conversion characteristic Ideal conversion characteristic V'[000]h Analog input Differential linearity error Ideal conversion characteristic Actual conversion characteristic V'[N]h V'[N]h - V'[N-1]h Differential linearity error E - 1 [LSB] 1LSB' V'[N-1]h Analog input EPSON S1C33L03 PRODUCT PART A-77...

  • Page 94: Ac Characteristics

    High level = 1/2 V Low level = 1/2 V Input signal waveform: Rise time (10% 90% V ) 5 ns Fall time (90% 10% V ) 5 ns Output load capacitance: C = 50 pF EPSON A-78 S1C33L03 PRODUCT PART...

  • Page 95: C33 Block Ac Characteristic Tables

    Item Symbol Min. Max. Unit BCLK clock output duty 3) 2.0 V single power source (Unless otherwise specified: V =2.0V 0.2V, V =0V, Ta=-40°C to +85°C) Item Symbol Min. Max. Unit BCLK clock output duty EPSON S1C33L03 PRODUCT PART A-79...
  • Page 96 Write data delay time (2) WDD2 Write data hold time note 1) This applies to the #BSH and #BSL timings. 2) This applies to the #GAAS and #GARD timings. 3) This applies to the #GAAS timing. EPSON A-80 S1C33L03 PRODUCT PART...
  • Page 97 Write signal pulse width (1+WC)-10 3) 2.0 V single power source (Unless otherwise specified: V =2.0V 0.2V, V =0V, Ta=-40°C to +85°C) Item Symbol Min. Max. Unit Write signal delay time (2) WRD2 Write signal pulse width (1+WC)-20 EPSON S1C33L03 PRODUCT PART A-81...
  • Page 98 #CAS signal delay time (2) CASD2 #CAS signal pulse width (0.5+WC)-20 CASW Read signal delay time (3) RDD3 Read signal pulse width (2) (2+WC)-20 RDW2 Write signal delay time (3) WRD3 Write signal pulse width (2) (2+WC)-20 WRW2 EPSON A-82 S1C33L03 PRODUCT PART...
  • Page 99 (Unless otherwise specified: V =2.0V 0.2V, V =0V, Ta=-40°C to +85°C) Item Symbol Min. Max. Unit Column address access time (1.5+WC)-60 ACCE #RAS access time (2+WC)-60 RACE #CAS access time (1+WC)-60 CACE Read data setup time RDS2 EPSON S1C33L03 PRODUCT PART A-83...
  • Page 100 #SDWE signal delay time (2) T+11 (WEDx2)p Read data setup time (14) (RDSx2) Read data hold time (RDHx2) Write data delay time (WDDx2) Write data hold time T+11 (WDHx2) Note: "T" indicates one cycle time of the CPU clock. EPSON A-84 S1C33L03 PRODUCT PART...
  • Page 101 =0V, Ta=-40°C to +85°C) Item Symbol Min. Max. Unit #BUSREQ signal setup time BRQS #BUSREQ signal hold time BRQH #BUSACK signal output delay time BAKD High-impedance output delay time Output high-impedance delay time #NMI pulse width NMIW EPSON S1C33L03 PRODUCT PART A-85...
  • Page 102 =2.0V 0.2V, V =0V, Ta=-40°C to +85°C) Item Symbol Min. Max. Unit Input data setup time INPS Input data hold time INPH Output data delay time OUTD K-port interrupt SLEEP, HALT2 mode KINW input pulse width Others EPSON A-86 S1C33L03 PRODUCT PART...

  • Page 103: C33 Block Ac Characteristic Timing Charts

    8.6.4 C33 Block AC Characteristic Timing Charts Clock (1) When an external clock is input (in x1 speed mode): OSC3 C3ED (High-speed clock) BCLK (Clock output) (2) When the high-speed oscillation circuit is used for the operating clock: BCLK (Clock output) EPSON S1C33L03 PRODUCT PART A-87...
  • Page 104 SRAM read cycle (when a wait cycle is inserted) (wait cycle) (last cycle) BCLK A[23:0] #CEx (C1 only) RDD1 RDD2 CEAC1 ACC1 RDAC1 D[15:0] #WAIT is measured with respect to the first signal change (negation) from among the #RD, #CEx and A[23:0] signals. EPSON A-88 S1C33L03 PRODUCT PART...
  • Page 105 A[23:0] #CEx WRD1 WRD2 WDD1 D[15:0] #WAIT SRAM write cycle (when wait cycles are inserted) (wait cycle) (wait cycle) (last cycle) Wait cycle follows Last cycle follows BCLK A[23:0] #CEx WRD1 WRD2 WDD1 D[15:0] #WAIT EPSON S1C33L03 PRODUCT PART A-89...
  • Page 106 #HCAS/ #LCAS RDD1 RDD3 RDW2 CACF ACCF RACF ACCF D[15:0] WRD1 WRD3 WRW2 WDD1 WDD2 WDD2 D[15:0] is measured with respect to the first signal change (negation) of either the #RD or the A[23:0] signals. EPSON A-90 S1C33L03 PRODUCT PART...
  • Page 107 RDD1 RDD3 RDW2 ACCE CACE RACE ACCE D[15:0] WRD1 WRD3 WRW2 WDD1 WDD2 WDD2 D[15:0] is measured with respect to the first signal change from among the #RD (negation), #RASx (negation) and #CAS (fall) signals. EPSON S1C33L03 PRODUCT PART A-91...
  • Page 108 (1) #X2SPD = high (CPU clock : SDRAM clock = 1 : 1) OSC3 (High-speed clock) BCLK (SDRAM clock output) (2) #X2SPD = low (CPU clock : SDRAM clock = 2 : 1) BCLK (SDRAM clock output) EPSON A-92 S1C33L03 PRODUCT PART...
  • Page 109 Read: CAS latency = 2, burst length = 2 Write: single write SDRAM mode-register-set cycle Mode register set BCLK SDCKE A[23:0] valid SDA10 valid CED1 CED2 #SDCEx RASD1 RASD2 #SDRAS CASD1 CASD2 #SDCAS WED1 WED2 #SDWE D[15:0] HDQM/ LDQM EPSON S1C33L03 PRODUCT PART A-93...
  • Page 110 Enter self refresh mode Exit self refresh mode BCLK CKE1 CKE2 SDCKE A[23:0] SDA10 CED1 CED2 #SDCEx RASD1 #SDRAS CASD1 #SDCAS WED1 #SDWE D[15:0] HDQM/ LDQM A precharge cycle is necessary before entering the self refresh mode. EPSON A-94 S1C33L03 PRODUCT PART...
  • Page 111 A[23:0], #RD, #WRL, #WRH, #HCAS, #LCAS, #CE[17:4], D[15:0] Input, output and I/O port timing BCLK INPS INPH Kxx, Pxx (input: data read Valid input from the port) OUTD Pxx, Rxx (output) KINW (K-port interrupt input) EPSON S1C33L03 PRODUCT PART A-95...

  • Page 112: Lcd Interface Ac Characteristics

    Power Save active to LCDPWR inactive Frame Power Save active to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY Frame inactive LPWREN = "1" to LCDPWR active Frame (when FP signals are active) LPWREN = "0" to LCDPWR inactive Frame EPSON A-96 S1C33L03 PRODUCT PART...
  • Page 113 VNDP = Vertical Non-Display Period = VNDP[5:0] (lines) VNDP[5:0] (D[5:0]/0x39FFEA) = Horizontal Display Period = (LDHSIZE[5:0] + 1) 16 (Ts) LDHSIZE[5:0] (D[5:0]/0x39FFE4) HNDP = Horizontal Non-Display Period = (HNDP[4:0] + 4) 8 (Ts) HNDP[4:0] (D[4:0]/0x39FFE7) EPSON S1C33L03 PRODUCT PART A-97...
  • Page 114 = pixel clock period - 9 (Ts) 1min 3min = (LDHSIZE[5:0] + 1) 16 + (HNDP[4:0] + 4) 8 (Ts) 3min = HNDP[4:0] 8 + 2 (Ts) 6min = HNDP[4:0] 8 + 11 (Ts) 7min EPSON A-98 S1C33L03 PRODUCT PART...
  • Page 115 VNDP = Vertical Non-Display Period = VNDP[5:0] (lines) VNDP[5:0] (D[5:0]/0x39FFEA) = Horizontal Display Period = (LDHSIZE[5:0] + 1) 16 (Ts) LDHSIZE[5:0] (D[5:0]/0x39FFE4) HNDP = Horizontal Non-Display Period = (HNDP[4:0] + 4) 8 (Ts) HNDP[4:0] (D[4:0]/0x39FFE7) EPSON S1C33L03 PRODUCT PART A-99...
  • Page 116 = pixel clock period - 9 (Ts) 1min 3min = (LDHSIZE[5:0] + 1) 16 + (HNDP[4:0] + 4) 8 (Ts) 3min = HNDP[4:0] 8 + 4 (Ts) 6min = HNDP[4:0] 8 + 13 (Ts) 7min EPSON A-100 S1C33L03 PRODUCT PART...
  • Page 117 VNDP = Vertical Non-Display Period = VNDP[5:0] (lines) VNDP[5:0] (D[5:0]/0x39FFEA) = Horizontal Display Period = (LDHSIZE[5:0] + 1) 16 (Ts) LDHSIZE[5:0] (D[5:0]/0x39FFE4) HNDP = Horizontal Non-Display Period = (HNDP[4:0] + 4) 8 (Ts) HNDP[4:0] (D[4:0]/0x39FFE7) EPSON S1C33L03 PRODUCT PART A-101...
  • Page 118 = pixel clock period - 9 (Ts) 1min 3min = (LDHSIZE[5:0] + 1) 16 + (HNDP[4:0] + 4) 8 (Ts) 3min = HNDP[4:0] 8 + 1.5 (Ts) 6min = HNDP[4:0] 8 + 10.5 (Ts) 7min EPSON A-102 S1C33L03 PRODUCT PART...
  • Page 119 VNDP = Vertical Non-Display Period = VNDP[5:0] (lines) VNDP[5:0] (D[5:0]/0x39FFEA) = Horizontal Display Period = (LDHSIZE[5:0] + 1) 16 (Ts) LDHSIZE[5:0] (D[5:0]/0x39FFE4) HNDP = Horizontal Non-Display Period = (HNDP[4:0] + 4) 8 (Ts) HNDP[4:0] (D[4:0]/0x39FFE7) EPSON S1C33L03 PRODUCT PART A-103...
  • Page 120 3min = HNDP[4:0] 8 + t + 1 (Ts) 6amin = HNDP[4:0] 8 + t + 1 (Ts) 6bmin = HNDP[4:0] 8 + 11 (Ts) 7amin = HNDP[4:0] 8 + 11 - t (Ts) 7bmin EPSON A-104 S1C33L03 PRODUCT PART...
  • Page 121 VNDP = Vertical Non-Display Period = VNDP[5:0] (lines) VNDP[5:0] (D[5:0]/0x39FFEA) = Horizontal Display Period = (LDHSIZE[5:0] + 1) 16 (Ts) LDHSIZE[5:0] (D[5:0]/0x39FFE4) HNDP = Horizontal Non-Display Period = (HNDP[4:0] + 4) 8 (Ts) HNDP[4:0] (D[4:0]/0x39FFE7) EPSON S1C33L03 PRODUCT PART A-105...
  • Page 122 = pixel clock period - 9 (Ts) 1min 3min = (LDHSIZE[5:0] + 1) 16 + (HNDP[4:0] + 4) 8 + 1 (Ts) 3min = HNDP[4:0] 8 + 1 (Ts) 6min = HNDP[4:0] 8 + 10 (Ts) 7min EPSON A-106 S1C33L03 PRODUCT PART...

  • Page 123: Oscillation Characteristics

    Operating temperature =2.7V to 3.6V °C =1.9V to 2.2V °C =1.8V to 2.2V °C #1 Q11C02RX: Crystal resonator made by Seiko Epson #2 "C =15pF" includes board capacitance. (Unless otherwise specified: V =3.3V, V =0V, crystal=Q11C02RX 32.768kHz, =20M , C =15pF , Ta=25°C)

  • Page 124: Pll Characteristics

    Symbol Condition Min. Typ. Max. Unit Jitter (peak jitter) Lockup time #1 Q3204DC: Crystal oscillator made by Seiko Epson (Unless otherwise specified: V =2.0V 0.2V, V =0V, crystal oscillator=Q3204DC =4.7k , C =100pF, C =5pF, Ta=-40°C to +85°C) Item Symbol Condition Min.

  • Page 125: Package

    This thermal resistance is a value under the condition that the measured device is hanging in the air and has no air-cooling. Thermal resistance greatly varies according to the mounting condition on the board and air- cooling condition. EPSON S1C33L03 PRODUCT PART A-109...

  • Page 126: Pad Layout

    10 PAD LAYOUT 10 Pad Layout 10.1 Pad Layout Diagram Die No. (0, 0) 5.97 mm EPSON A-110 S1C33L03 PRODUCT PART...

  • Page 127: Pad Coordinate

    -1870.0 P16/EXCL5/#DMAEND1/SOUT3 770.0 2549.5 K52/#ADTRG 2843.5 -1760.0 P15/EXCL4/#DMAEND0/#SCLK3/LDQM 660.0 2549.5 K51/#DMAREQ1 2843.5 -1650.0 A0/#BSL 550.0 2549.5 K50/#DMAREQ0 2843.5 -1540.0 A1/SDA0 440.0 2549.5 #WRH/#BSH 2843.5 -1430.0 A2/SDA1 330.0 2549.5 #WRL/#WR/#WE 2843.5 -1320.0 100 A3/SDA2 220.0 2549.5 EPSON S1C33L03 PRODUCT PART A-111...
  • Page 128 1760.0 156 P03/#SRDY0 -2843.5 -1540.0 127 PLLS1 -2843.5 1650.0 157 P02/#SCLK0 -2843.5 -1650.0 128 PLLS0 -2843.5 1540.0 158 N.C. -2843.5 -1760.0 129 V -2843.5 1430.0 159 P01/SOUT0 -2843.5 -1870.0 130 PLLC -2843.5 1320.0 160 P00/SIN0 -2843.5 -1980.0 EPSON A-112 S1C33L03 PRODUCT PART...

  • Page 129: Appendix A External Device Interface Timings

    Conditions such as the output delay time of the device, delay due to wiring and load capacitance, and input setup time are not considered. • The described contents are reference data and cannot be guaranteed to work. EPSON S1C33L03 PRODUCT PART A-113...

  • Page 130: Dram (70Ns

    Fast-page mode #CAS precharge time – Access time after #CAS precharge <Refresh cycle> – #CAS setup time – #CAS hold time – #RAS precharge #CAS hold time 10000 #RAS pulse width (only in refresh cycle) EPSON A-114 S1C33L03 PRODUCT PART...
  • Page 131 COL #1 COL #2 #RAS #CAS D[15:0](RD) RD data RD data D[15:0](WR) WR data WR data DRAM: 70ns, CPU: 33MHz, CAS-before-RAS refresh cycle RPC delay Fixed Refresh RAS pulse width RAS precharge BCLK #RAS #CAS EPSON S1C33L03 PRODUCT PART A-115...
  • Page 132 COL #1 COL #2 #RAS #CAS D[15:0](RD) RD data RD data D[15:0](WR) WR data WR data DRAM: 70ns, CPU: 25/20MHz, CAS-before-RAS refresh cycle RPC delay Fixed Refresh RAS pulse width RAS precharge BCLK #RAS #CAS EPSON A-116 S1C33L03 PRODUCT PART...

  • Page 133: Dram (60Ns

    Fast-page mode #CAS precharge time – Access time after #CAS precharge <Refresh cycle> – #CAS setup time – #CAS hold time – #RAS precharge #CAS hold time 10000 #RAS pulse width (only in refresh cycle) EPSON S1C33L03 PRODUCT PART A-117...
  • Page 134 COL #1 COL #2 #RAS #CAS D[15:0](RD) RD data RD data D[15:0](WR) WR data WR data DRAM: 60ns, CPU: 33MHz, CAS-before-RAS refresh cycle RPC delay Fixed Refresh RAS pulse width RAS precharge BCLK #RAS #CAS EPSON A-118 S1C33L03 PRODUCT PART...
  • Page 135 COL #1 COL #2 #RAS #CAS D[15:0](RD) RD data RD data D[15:0](WR) WR data WR data DRAM: 60ns, CPU: 25MHz, CAS-before-RAS refresh cycle RPC delay Fixed Refresh RAS pulse width RAS precharge BCLK #RAS #CAS EPSON S1C33L03 PRODUCT PART A-119...
  • Page 136 COL #1 COL #2 #RAS #CAS D[15:0](RD) RD data RD data D[15:0](WR) WR data WR data DRAM: 60ns, CPU: 20MHz, CAS-before-RAS refresh cycle RPC delay Fixed Refresh RAS pulse width RAS precharge BCLK #RAS #CAS EPSON A-120 S1C33L03 PRODUCT PART...

  • Page 137: Rom And Burst Rom

    ROM: 100ns, CPU: 33MHz, normal read BCLK A[23:0] #CE9, 10 D[15:0] RD data ROM: 100ns, CPU: 33MHz, burst read BCLK Normal read cycle Burst read cycle A[23:0] #CE9, 10 RD data RD data RD data RD data D[15:0] EPSON S1C33L03 PRODUCT PART A-121...
  • Page 138 ROM: 100ns, CPU: 20MHz, normal read BCLK A[23:0] #CE9, 10 D[15:0] RD data ROM: 100ns, CPU: 20MHz, burst read BCLK Normal read cycle Burst read cycle A[23:0] #CE9, 10 RD data RD data RD data RD data D[15:0] EPSON A-122 S1C33L03 PRODUCT PART...

  • Page 139: Sram (55Ns

    Write pulse width – Input data setup time – Input data hold time SRAM: 55ns, CPU: 33/25MHz, read cycle BCLK A[23:0] #CEx RD data D[15:0] SRAM: 55ns, CPU: 33/25MHz, write cycle BCLK A[23:0] #CEx D[15:0] WR data EPSON S1C33L03 PRODUCT PART A-123...
  • Page 140 APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS SRAM: 55ns, CPU: 20MHz, read cycle BCLK A[23:0] #CEx RD data D[15:0] SRAM: 55ns, CPU: 20MHz, write cycle BCLK A[23:0] #CEx D[15:0] WR data EPSON A-124 S1C33L03 PRODUCT PART...

  • Page 141: Sram (70Ns

    Write pulse width – Input data setup time – Input data hold time SRAM: 70ns, CPU: 33MHz, read cycle BCLK A[23:0] #CEx RD data D[15:0] SRAM: 70ns, CPU: 33MHz, write cycle BCLK A[23:0] #CEx D[15:0] WR data EPSON S1C33L03 PRODUCT PART A-125...
  • Page 142 APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS SRAM: 70ns, CPU: 25/20MHz, read cycle BCLK A[23:0] #CEx RD data D[15:0] SRAM: 70ns, CPU: 25/20MHz, write cycle BCLK A[23:0] #CEx D[15:0] WR data EPSON A-126 S1C33L03 PRODUCT PART...

  • Page 143: 8255A

    3 If the data hold time that can be set is not sufficient for the device, secure it by connecting a bus repeater to the external data bus D[15:0] or by inserting a latch at the output side of the external system interface. EPSON S1C33L03 PRODUCT PART...

  • Page 144: Appendix B Pin Characteristics

    Pull-up K50/#DMAREQ0 XHIBHP2 CMOS/LVTTL SCHMITT Pull-up #WRH/#BSH XHBC1T note 3 Type1 #WRL/#WR/#WE XHBC1T note 3 Type1 XHBC1T note 3 Type1 XHBC1T CMOS/LVTTL Type1 XHBC1T CMOS/LVTTL Type1 XHBC1T CMOS/LVTTL Type1 XHBC1T CMOS/LVTTL Type1 XHBC1T CMOS/LVTTL Type1 EPSON A-128 S1C33L03 PRODUCT PART...
  • Page 145 A7/SDA6 XHBC1T note 3 Type1 A8/SDA7 XHBC1T note 3 Type1 A9/SDA8 XHBC1T note 3 Type1 A10/SDA9 XHBC1T note 3 Type1 XHBC1T note 3 Type1 A12/SDA11 XHBC1T note 3 Type1 100 A13/SDA12 XHBC1T note 3 Type1 EPSON S1C33L03 PRODUCT PART A-129...
  • Page 146 The following table lists output current characteristics. Output current (I 5.0 V 3.3 V 2.0 V Type1 3 mA 2 mA 0.6 mA Type2 – 6 mA 2 mA Type3 12 mA 12 mA 4 mA EPSON A-130 S1C33L03 PRODUCT PART...
  • Page 147 S1C33L03 FUNCTION PART...

  • Page 149: Ioutline

    S1C33L03 FUNCTION PART I OUTLINE...

  • Page 151: Introduction

    I OUTLINE: INTRODUCTION I-1 INTRODUCTION The Function Part gives a detailed description of the various function blocks built into the Seiko Epson original 32-bit microcomputer S1C33L03. The S1C33L03 employs a RISC type CPU, and has a powerful instruction set capable of compilation into compact code, despite the small CPU core size.
  • Page 152 I OUTLINE: INTRODUCTION THIS PAGE IS BLANK. EPSON B-I-1-2 S1C33L03 FUNCTION PART...

  • Page 153: Block Diagram

    C33 Core Block C33_ADC C33_PERI Pads (A/D converter) (Prescaler, 8-bit timer, 16-bit timer, Clock timer, Serial interface, Ports) C33 Analog Block C33 Peripheral Block Figure 2.1 Block Configuration Note: Internal ROM is not provided in the S1C33L03. EPSON S1C33L03 FUNCTION PART B-I-2-1...
  • Page 154 The LCD Controller Block provides LCD control signals for a 4- or 8-bit color/monochrome LCD panel. C33 Memory Block The S1C33L03 contains an 8KB of SRAM as the internal memory. For details of the blocks, refer to the respective section in this manual. EPSON B-I-2-2 S1C33L03 FUNCTION PART...

  • Page 155: List Of Pins

    Write (low byte) signal when SBUSST(D3/0x4812E) = "0" (default) #WR: Write signal when SBUSST(D3/0x4812E) = "1" #WE: DRAM write signal #WRH – #WRH: Write (high byte) signal when SBUSST(D3/0x4812E) = "0" (default) #BSH #BSH: Bus strobe (high byte) signal when SBUSST(D3/0x4812E) = "1" EPSON S1C33L03 FUNCTION PART B-I-3-1...
  • Page 156 Area read signal output for GA when CFEX3(D3/0x402DF) = "1" GPIO2: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and BREQEN(D2/0x39FFFD) = "0" EA10MD1 Pull-up Area 10 boot mode selection EA10MD1 EA10MD0 Mode EA10MD0 – External ROM mode Internal ROM mode EPSON B-I-3-2 S1C33L03 FUNCTION PART...
  • Page 157 I/O port when CFP07(D7/0x402D0) = "0" and CFEX7(D7/0x402DF) = "0" #SRDY1 (default) #DMAEND3 #SRDY1: Serial I/F Ch. 1 ready signal output when CFP07(D7/0x402D0) = "1" and CFEX5(D5/0x402DF) = "0" #DMAEND3: HSDMA Ch. 3 end-of-transfer signal output when CFEX7(D7/0x402DF) = "1" EPSON S1C33L03 FUNCTION PART B-I-3-3...
  • Page 158 16-bit timer 0 event counter input when CFP10(D0/0x402D4) = "1", T8UF0 IOC10(D0/0x402D6) = "0" and CFEX1(D1/0x402DF) = "0" DST0 T8UF0: 8-bit timer 0 output when CFP10(D0/0x402D4) = "1", IOC10(D0/0x402D6) = "1" and CFEX1(D1/0x402DF) = "0" DST0: DST0 signal output when CFEX1(D1/0x402DF) = "1" (default) EPSON B-I-3-4 S1C33L03 FUNCTION PART...
  • Page 159 CFP24(D4/0x402D8) = "0" – P25: I/O port when CFP25(D5/0x402D8) = "0" (default) TM3: 16-bit timer 3 output when CFP25(D5/0x402D8) = "1" #SCLK2 #SCLK2: Serial I/F Ch. 2 clock input/output when SSCLK2(D2/0x402DB) = "1" and CFP25(D5/0x402D8) = "0" EPSON S1C33L03 FUNCTION PART B-I-3-5...
  • Page 160 – P35: I/O port when CFP35(D5/0x402DC) = "0" (default) #BUSACK #BUSACK: Bus acknowledge output when CFP35(D5/0x402DC) = "1" and GPIO1 CFP34(D4/0x402DC) = "1" GPIO1: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and BREQEN(D2/0x39FFFD) = "0" EPSON B-I-3-6 S1C33L03 FUNCTION PART...
  • Page 161 1: CPU clock = bus clock 1, 0: CPU clock = bus clock #NMI Pull-up NMI request input pin #RESET Pull-up Initial reset input pin Note: "#" in the pin names indicates that the signal is low active. EPSON S1C33L03 FUNCTION PART B-I-3-7...
  • Page 162 I OUTLINE: LIST OF PINS THIS PAGE IS BLANK. EPSON B-I-3-8 S1C33L03 FUNCTION PART...

  • Page 163: Core Block

    S1C33L03 FUNCTION PART II CORE BLOCK...

  • Page 165: Introduction

    C33 Core Block C33_ADC C33_PERI Pads (A/D converter) (Prescaler, 8-bit timer, 16-bit timer, Clock timer, Serial interface, Ports) C33 Analog Block C33 Peripheral Block Figure 1.1 Core Block Note: Internal ROM is not provided in the S1C33L03. EPSON S1C33L03 FUNCTION PART B-II-1-1...
  • Page 166 II CORE BLOCK: INTRODUCTION THIS PAGE IS BLANK. EPSON B-II-1-2 S1C33L03 FUNCTION PART...

  • Page 167: Cpu And Operating Mode

    User Logic Block. Refer to the "S1C33000 Core CPU Manual" for details of the S1C33000. B-II EPSON S1C33L03 FUNCTION PART B-II-2-1...

  • Page 168: Standby Mode

    Note that SLEEP mode cannot be canceled with an interrupt factor except for reset and NMI if the PSR is set into interrupt disabled status. EPSON B-II-2-2 S1C33L03 FUNCTION PART...

  • Page 169: Notes On Standby Mode

    In the debug mode, the OSC3 clock is used as the CPU operating clock. Therefore, do not stop the high-speed (OSC3) oscillation circuit when using the debugging functions. Furthermore, only the CPU and BCU operate in the debug mode, and other internal peripheral circuits (except the oscillation circuit) stop operating. EPSON S1C33L03 FUNCTION PART B-II-2-3...

  • Page 170: Trap Table

    – – 50(Base+C8) 16-bit programmable timer 5 Timer 5 comparison B 51(Base+CC) Timer 5 comparison A 52(Base+D0) 8-bit programmable timer Timer 0 underflow 53(Base+D4) Timer 1 underflow 54(Base+D8) Timer 2 underflow 55(Base+DC) Timer 3 underflow EPSON B-II-2-4 S1C33L03 FUNCTION PART...
  • Page 171 Edge (rising or falling) or level (High or Low) 71(Base+11C) Port input interrupt 7 Edge (rising or falling) or level (High or Low) Base = Set value in the TTBR register (0x48134 to 0x48137); 0xC00000 by default. B-II EPSON S1C33L03 FUNCTION PART B-II-2-5...
  • Page 172 II CORE BLOCK: CPU AND OPERATING MODE THIS PAGE IS BLANK. EPSON B-II-2-6 S1C33L03 FUNCTION PART...

  • Page 173: Initial Reset

    #NMI must be set to high longer than #NMI must be set to low longer than the reset pulse width. the reset pulse width. (1) Cold start (2) Hot start Figure 3.1 Setup of #RESET and #NMI Pins EPSON S1C33L03 FUNCTION PART B-II-3-1...

  • Page 174: Power-On Reset

    To reset the chip when the high-speed (OSC3) oscillation circuit is in off status, the pulse width must be extended until the oscillation stabilizes similarly to the power-on reset. Be aware that a short reset pulse may cause an operation error. EPSON B-II-3-2 S1C33L03 FUNCTION PART...

  • Page 175: Boot Address

    (cold start or hot start). Therefore, it is necessary to set up the peripheral circuit conditions. Refer to the I/O maps or explanation of each peripheral circuit section for initial settings of the peripheral circuits. EPSON S1C33L03 FUNCTION PART B-II-3-3...
  • Page 176 II CORE BLOCK: INITIAL RESET THIS PAGE IS BLANK. EPSON B-II-3-4 S1C33L03 FUNCTION PART...

  • Page 177: Bcu (Bus Control Unit)

    / Serial I/F Ch. 3 clock input/output / SDRAM data (low byte) input/output mask signal output #X2SPD CPU - BCLK clock ratio 1: CPU clock = Bus clock, 0: CPU clock = Bus clock x 2 EA10MD[1:0] Area 10 boot mode selection 11: External ROM, 10: Internal ROM EPSON S1C33L03 FUNCTION PART B-II-4-1...
  • Page 178 The user logic can also be used as input ports with these signals. The internal bus signals are available when an internal access area is set using the BCU register. The bus conditions can be programmed using the BCU registers similar to the external bus. EPSON B-II-4-2 S1C33L03 FUNCTION PART...

  • Page 179: Combination Of System Bus Control Signals

    1 In the #BSL system, the A0 and #WRH pin functions change according to the endian selected (little endian or big endian). When using DRAM, the #CE output pins in areas 7–8 (areas 13–14) function as the #RAS1–2 (#RAS3–4) pins. EPSON S1C33L03 FUNCTION PART B-II-4-3...

  • Page 180: Memory Area

    Note: Addresses 0x39FFC0–0x39FFCD in Area 6 are reserved as the internal memory area for the control I/O memory of the SDRAM controller. Pay attention to this area since it must be accessed when controlling the SDRAM self-refresh mode or other SDRAM functions. EPSON B-II-4-4 S1C33L03 FUNCTION PART...

  • Page 181: External Memory Map And Chip Enable

    Area 4 (#CE4) 0x01FFFFF 0x03FFFFF External I/O (16-bit device) SRAM type SRAM type 0x0380000 External memory 1 (1MB) 8 or 16 bits 0x037FFFF External I/O (8-bit device) 0x0100000 0x0300000 CEFUNC = "00" CEFUNC = "01" EPSON S1C33L03 FUNCTION PART B-II-4-5...
  • Page 182 The P30 and P34 terminals are set for the general I/O ports at initial reset. The P30 and P34 terminals are shared with the #WAIT input and the #BUSREQ input, respectively. Therefore, when using the #WAIT and #BUSREQ signals, these terminals cannot be used for #CE4+#CE5 and #CE6 outputs. EPSON B-II-4-6 S1C33L03 FUNCTION PART...

  • Page 183: Using Internal Memory On External Memory Area

    CFEX3 (D3)/Port function extension register (0x402DF) = "1" These signals are common used to all the above areas, so when two or more areas are selected to output the exclusive signal, OR condition is applied. EPSON S1C33L03 FUNCTION PART B-II-4-7...

  • Page 184: Area 10

    A10IR[2:0] (D[E:C)/Areas 10–9 set-up register (0x48126). Table 4.7 Area 10 Internal ROM Size A10IR2 A10IR1 A10IR0 ROM size 16 KB 32 KB 64 KB 128 KB 256 KB 512 KB 1 MB 2 MB (default) EPSON B-II-4-8 S1C33L03 FUNCTION PART...

  • Page 185: Area 3

    Area 3 is reserved for S1C33 middleware. To use this area, external emulation memory is used. When external emulation memory is used, A3EEN (DB/0x48130) must be set to "1". Table 4.8 Area 3 Mode Selection A3EEN Area 3 mode Emulation mode Unused EPSON S1C33L03 FUNCTION PART B-II-4-9...

  • Page 186: Setting External Bus Conditions

    Note: The BCU supports 16-bit burst ROM. Therefore, when connecting burst ROM to area 10 or area 9, do not set the device size to 8 bits (A10SZ = "1"). For differences in bus operation due to the device size and access data size, refer to "Bus Operation of External Memory". EPSON B-II-4-10 S1C33L03 FUNCTION PART...

  • Page 187: Setting Sram Timing Conditions

    If the number of wait cycles set is 2 or more, the bus cycle is actually extended. In this case, the bus write cycle consists of [number of wait cycles + 1], as in the case of read cycles (providing that there is no external wait). EPSON S1C33L03 FUNCTION PART B-II-4-11...

  • Page 188: Setting Timing Conditions Of Burst Rom

    RBST8 (DD) / Bus control register (0x4812E) is used for this selection. The eight-consecutive-burst mode is selected by writing "1" to RBST8 and the four-consecutive-burst mode is selected by setting the bit to "0". At cold start, the four-consecutive-burst mode is set by default. EPSON B-II-4-12 S1C33L03 FUNCTION PART...

  • Page 189: Bus Operation

    (1) For data reads, the operation is as shown in the figure below. (2) For little-endian data writes, read A0 as #BSC, and #WRH as #BSH. (3) For big-endian data writes, read A0 as #BSL, and #WRL as #BSH. EPSON S1C33L03 FUNCTION PART B-II-4-13...
  • Page 190 Destination (general-purpose register) Bus operation Sign or Zero extension Byte 1 Byte 0 Data bus #WRH #WRL Byte 1 Byte 0 A[1:0]= 0 Source (16-bit device) Figure 4.8 Half-word Data Reading from a 16-bit Device EPSON B-II-4-14 S1C33L03 FUNCTION PART...
  • Page 191 Byte 1 Byte 0 Data bus #WRH #WRL Byte 3 Ignored Byte 2 Ignored A[1:0]=00 A[1:0]=01 A[1:0]=10 A[1:0]=11 Byte 1 Ignored Source (8-bit device) Byte 0 Ignored Figure 4.12 Word Data Reading from an 8-bit Device EPSON S1C33L03 FUNCTION PART B-II-4-15...
  • Page 192 Source (8-bit device) Big-endian Destination (general-purpose register) Bus operation Sign or Zero extension Byte 0 Data bus #WRH #WRL Byte 0 Ignored A[1:0]= Source (8-bit device) Figure 4.16 Byte Data Reading from an 8-bit Device EPSON B-II-4-16 S1C33L03 FUNCTION PART...

  • Page 193: Bus Clock

    SD_CLK (SDRCLK = "1") SD_CLK (SDRCLK = "0") SDCKE Self refresh 1 Access to the internal RAM 2 Access to the external memory (other than SDRAM) 3 Access to the SDRAM Figure 4.17 Clock System EPSON S1C33L03 FUNCTION PART B-II-4-17...

  • Page 194: Bus Speed Mode

    SDRAM control register (0x39FFC1). Table 4.14 Selection of BCLK Output Clock SDRENA BCLKSEL1 BCLKSEL0 Output clock PLL_CLK (PLL output clock) OSC3_CLK (OSC3 oscillation clock) BCU_CLK (BCU operating clock) CPU_CLK (CPU operating clock) – – SD_CLK (SDRAM clock) EPSON B-II-4-18 S1C33L03 FUNCTION PART...

  • Page 195: Bus Cycles In External System Interface

    (high level), the read cycle is terminated. Note: Insertion of wait cycles via the #WAIT pin is possible only when the device for bus conditions is set for SRAM, and SWAITE (D0) / Bus control register (0x4812E) is enabled for waiting. EPSON S1C33L03 FUNCTION PART B-II-4-19...

  • Page 196: Bus Timing

    With an output disable cycle, there is normally a gap between one read cycle and the next. Note, however, that this output disable cycle is not inserted in the case of consecutive reads in a memory area for which the same chip enable signal is output. EPSON B-II-4-20 S1C33L03 FUNCTION PART...

  • Page 197: Sram Write Cycles

    Figure 4.23 Byte Write Cycle with No Wait (A0 system, little endian) BCLK addr A[23:0] #CExx #BSH #BSL #WRL Undefined Valid D[15:8] Valid Undefined D[7:0] Figure 4.24 Byte Write Cycle with No Wait (#BSL system, little endian) EPSON S1C33L03 FUNCTION PART B-II-4-21...
  • Page 198 In this case, the bus write cycle consists of [number of wait cycles + 1], as in the case of read cycles (providing that there is no external wait). EPSON B-II-4-22 S1C33L03 FUNCTION PART...

  • Page 199: Burst Rom Read Cycles

    If area 10 or 9 is set for burst ROM, a SRAM write cycle is executed when a write to that area is attempted. In this case, wait cycles via the #WAIT pin can be inserted. EPSON S1C33L03 FUNCTION PART...

  • Page 200: Dram Direct Interface

    (256K bytes) 5 DRAM (4M) DRAM (4M) 8M bits (1M bytes) 6 DRAM (16M) DRAM (16M) 32M bits (4M bytes) Also, the S1C33L03 provides an SDRAM direct interface. Refer to "VI SDRAM Controller Block" for details. EPSON B-II-4-24 S1C33L03 FUNCTION PART...

  • Page 201: Dram Setting Conditions

    If the successive RAS mode is suspended, a precharge cycle is inserted before the next bus cycle begins. Note: When using the successive RAS mode, always be sure to use #DRD for the read signal and #DWE for the low-byte write signal. EPSON S1C33L03 FUNCTION PART B-II-4-25...
  • Page 202 RPC2 to "0". If RPC1 is switched over when RPC2 = "1" (refresh enabled), an undesirable self-refresh cycle is generated. So be sure to clear RPC2 to "0" (refresh disabled) before selecting the refresh method. EPSON B-II-4-26 S1C33L03 FUNCTION PART...
  • Page 203 Use RASC to choose the number of RAS cycles when accessing DRAM. Table 4.22 Number of RAS Cycles RASC1 RASC0 Number of cycles 4 cycles 3 cycles 2 cycles 1 cycle The initial default value is 1 cycle. EPSON S1C33L03 FUNCTION PART B-II-4-27...

  • Page 204: Dram Read/Write Cycles

    BCLK COL #1 COL #2 A[11:0] #RASx #HCAS/ #LCAS data data D[15:0] Figure 4.31 DRAM Read Cycle (EDO page mode) The read timing in EDO page-mode lags 0.5 cycles behind that in fast page mode. EPSON B-II-4-28 S1C33L03 FUNCTION PART...
  • Page 205 Example: RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle; byte-write sample (little endian) Precharge RAS cycle CAS cycle #1 CAS cycle #2 cycle BCLK A[11:0] #RASx #HCAS #LCAS Undefined write data D[15:8] write data Undefined D[7:0] Figure 4.34 DRAM Byte-Write Cycle (fast page or EDO page mode) EPSON S1C33L03 FUNCTION PART B-II-4-29...
  • Page 206 • relinquishing of bus control is requested by an external bus master. Note: When using the successive RAS mode, always be sure to use #DRD for the read signal and #DWE for the low-byte write signal. EPSON B-II-4-30 S1C33L03 FUNCTION PART...

  • Page 207: Dram Refresh Cycles

    The refresh RAS pulse width is determined by the timing at which the refresh is deactivated in software and is unaffected by settings of RRA. #RAS and #HCAS/#LCAS are booted up simultaneously upon completion of a self-refresh and the precharge duration that follows is fixed at 6 cycles. EPSON S1C33L03 FUNCTION PART B-II-4-31...

  • Page 208: Releasing External Bus

    The DMA transfer that has been kept pending is restarted when the CPU gains control of the bus ownership. EPSON B-II-4-32 S1C33L03 FUNCTION PART...

  • Page 209: Power-Down Control By External Device

    #BUSREQ pin is released back high. Unlike in the case of ordinary releasing of the bus by #BUSREQ, the address bus and bus control signals are not placed in high-impedance state. For a DRAM refresh request that may arise in this HALT state, take one of the corrective measures described above. EPSON S1C33L03 FUNCTION PART B-II-4-33...

  • Page 210: I/O Memory Of Bcu

    1 8 bits 0 16 bits A14DF1 Areas 14–13 A14DF[1:0] Number of cycles A14DF0 output disable delay time – reserved – – – 0 when being read. A14WT2 Areas 14–13 wait control A14WT[2:0] Wait cycles A14WT1 A14WT0 EPSON B-II-4-34 S1C33L03 FUNCTION PART...
  • Page 211 1 8 bits 0 16 bits A8DF1 Areas 8–7 A8DF[1:0] Number of cycles A8DF0 output disable delay time – reserved – – – 0 when being read. A8WT2 Areas 8–7 wait control A8WT[2:0] Wait cycles A8WT1 A8WT0 EPSON S1C33L03 FUNCTION PART B-II-4-35...
  • Page 212 Writing 1 not allowed. SBUSST External interface method selection 1 #BSL 0 A0 SEMAS External bus master setup 1 Existing 0 Nonexistent SEPD External power-down control 1 Enabled 0 Disabled SWAITE #WAIT enable 1 Enabled 0 Disabled EPSON B-II-4-36 S1C33L03 FUNCTION PART...
  • Page 213 A1X1MD Area 1 access-speed 1 2 cycles 0 4 cycles x2 speed mode only – reserved – – 0 when being read. BCLKSEL1 BCLK output clock selection BCLKSEL[1:0] BCLK BCLKSEL0 PLL_CLK OSC3_CLK BCU_CLK CPU_CLK EPSON S1C33L03 FUNCTION PART B-II-4-37...
  • Page 214 AxxWT. Wait cycles derived from the #WAIT pin also can be inserted in the cycle for writing to the burst ROM area. At cold start, these bits are set to "111" (7 cycles). At hot start, the bits retain their status before being initialized. EPSON B-II-4-38 S1C33L03 FUNCTION PART...
  • Page 215 ROM write cycle. For the burst ROM write cycle, the wait cycles set via the #WAIT pin can also be used. At cold start, A10BW is set to "0" (no wait cycle). At hot start, A10BW retains its status before being initialized. EPSON S1C33L03 FUNCTION PART...
  • Page 216 The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM. At cold start, REDO is set to "0" (fast-page mode). At hot start, REDO retains its status before being initialized. EPSON B-II-4-40...
  • Page 217 The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM. At cold start, RPC0 is set to "0" (1 cycle). At hot start, RPC0 retains its status before being initialized. EPSON S1C33L03 FUNCTION PART...
  • Page 218 CPU is placed in a HALT state, allowing for reduction in power consumption. At cold start, SEPD is set to "0" (disabled). At hot start, SEPD retains its status before being initialized. EPSON B-II-4-42 S1C33L03 FUNCTION PART...
  • Page 219 Furthermore, when CEFUNC is set to "10" or "11", four chip enable signal is expanded into two area size. At cold start, CEFUNC is set to "00". At hot start, CEFUNC retains its status before being initialized. EPSON S1C33L03 FUNCTION PART...
  • Page 220 The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM. At cold start, RASC is set to "0" (1 cycle). At hot start, RASC retains its status before being initialized. EPSON B-II-4-44...
  • Page 221 If AxxAS is set to "0", the signal output is disabled. At cold start, these bits are set to "0" (disabled). At hot start, these bits retain their status before being initialized. EPSON S1C33L03 FUNCTION PART...
  • Page 222 4. When the CPU stops by the HALT or SLP instruction, this clock is also stopped. This clock is almost in phase with the bus clock. At initial reset, BCLKSEL is set to "00" (CPU_CLK). EPSON B-II-4-46 S1C33L03 FUNCTION PART...
  • Page 223 When x1 speed mode is set (#X2SPD pin = "1"), area 1 is always accessed in 2 cycles regardless of the A1X1MD value. At cold start, A1X1MD is set to "0" (4 cycles). At hot start, A1X1MD retains its status before being initialized. EPSON S1C33L03 FUNCTION PART B-II-4-47...
  • Page 224 II CORE BLOCK: BCU (Bus Control Unit) THIS PAGE IS BLANK. EPSON B-II-4-48 S1C33L03 FUNCTION PART...

  • Page 225: Itc (Interrupt Controller)

    Edge (rising or falling) or level (High or Low) 46 70(Base+118) Port input interrupt 6 Edge (rising or falling) or level (High or Low) 47 71(Base+11C) Port input interrupt 7 Edge (rising or falling) or level (High or Low) EPSON S1C33L03 FUNCTION PART B-II-5-1...
  • Page 226 The PSR and interrupt control register will be detailed later. For details about interrupt factor generating conditions, refer to the description of each peripheral circuit in this manual. EPSON B-II-5-2 S1C33L03 FUNCTION PART...

  • Page 227: Interrupt Factors And Intelligent Dma

    If an interrupt to be generated upon completion of IDMA is disabled at the setting of the IDMA side, no interrupt request is signaled to the CPU. Therefore, the CPU remains idle until the next interrupt request is generated. EPSON S1C33L03 FUNCTION PART B-II-5-3...

  • Page 228: Trap Table

    However, since an occurrence of NMI or the like between writes of the low-order and high-order half-words would cause a malfunction, it is recommended that the register be written in words. EPSON B-II-5-4 S1C33L03 FUNCTION PART...

  • Page 229: Control Of Maskable Interrupts

    IL is rewritten. The IL is restored to its previous status when the interrupt processing routine is terminated by the reti instruction. EPSON S1C33L03 FUNCTION PART B-II-5-5...

  • Page 230: Interrupt Factor Flag And Interrupt Enable Register

    For details about interrupt factor generating conditions, refer to the description of each peripheral circuit in this manual. EPSON B-II-5-6 S1C33L03 FUNCTION PART...
  • Page 231 These signals remain asserted until the interrupt factor flag is reset to "0" or the corresponding bit of the interrupt enable register is set to "0" (interrupts are disabled) or until some other interrupt factor of higher priority occurs. They are not cleared if the CPU simply accepts the interrupt request. EPSON S1C33L03 FUNCTION PART B-II-5-7...

  • Page 232: Interrupt Priority Register And Interrupt Levels

    However, if the interrupt level of the IL is set below the current level and the IE is set to enable interrupts before resetting the interrupt factor flag after an interrupt has occurred, the same interrupt may occur again. EPSON B-II-5-8 S1C33L03 FUNCTION PART...

  • Page 233: Idma Invocation

    An IDMA invocation request is accepted even when the interrupt enable register and PSR of the CPU is set to disable interrupts. It is also necessary that the control information for the IDMA channel has been set. EPSON S1C33L03 FUNCTION PART...
  • Page 234 Reset B signal (reset IDMA request bit) Reset C signal (reset IDMA enable bit) IDMA request bit "1" IDMA enable bit Figure 5.3 Sequence when DINTEN = "0" For details on IDMA, refer to "IDMA (Intelligent DMA)". EPSON B-II-5-10 S1C33L03 FUNCTION PART...

  • Page 235: Hsdma Invocation

    Before HSDMA can be invoked by the occurrence of an interrupt factor, it is necessary that DMA be enabled on the HSDMA side by setting the control register for HSDMA transfer. For details about HSDMA, refer to "HSDMA (High-Speed DMA)". EPSON S1C33L03 FUNCTION PART B-II-5-11...

  • Page 236: I/O Memory Of Interrupt Controller

    0 when being read. interrupt P16T32 16-bit timer 3 interrupt level 0 to 7 priority register P16T31 P16T30 – reserved – – – 0 when being read. P16T22 16-bit timer 2 interrupt level 0 to 7 P16T21 P16T20 EPSON B-II-5-12 S1C33L03 FUNCTION PART...
  • Page 237 – reserved – – – 0 when being read. E16TC2 16-bit timer 2 comparison A 1 Enabled 0 Disabled E16TU2 16-bit timer 2 comparison B D1–0 – reserved – – – 0 when being read. EPSON S1C33L03 FUNCTION PART B-II-5-13...
  • Page 238 0 No factor is flag register FSRX1 SIF Ch.1 receive buffer full generated generated FSERR1 SIF Ch.1 receive error FSTX0 SIF Ch.0 transmit buffer empty FSRX0 SIF Ch.0 receive buffer full FSERR0 SIF Ch.0 receive error EPSON B-II-5-14 S1C33L03 FUNCTION PART...
  • Page 239 DEP4 Port input 4 register – reserved – – – 0 when being read. DEADE A/D converter 1 IDMA 0 IDMA DESTX1 SIF Ch.1 transmit buffer empty enabled disabled DESRX1 SIF Ch.1 receive buffer full EPSON S1C33L03 FUNCTION PART B-II-5-15...
  • Page 240 IDMA enable register set method 1 Set only 0 RD/WR register selection IDMAONLY IDMA request register set method 1 Set only 0 RD/WR selection RSTONLY Interrupt factor flag reset method 1 Reset only 0 RD/WR selection EPSON B-II-5-16 S1C33L03 FUNCTION PART...
  • Page 241 Fixed at 0 0 when being read. order register (HW) TTBR32 Writing 1 not allowed. TTBR31 TTBR30 TTBR2B Trap table base address [27:16] 0x0C0 TTBR2A TTBR29 TTBR28 TTBR27 TTBR26 TTBR25 TTBR24 TTBR23 TTBR22 TTBR21 TTBR20 EPSON S1C33L03 FUNCTION PART B-II-5-17...
  • Page 242 For the interrupt factors used to request IDMA invocation or clear the standby mode, the corresponding interrupt enable register bit must be set for interrupt enable. When initially reset, this register is set to "0" (interrupt disabled). EPSON B-II-5-18 S1C33L03 FUNCTION PART...
  • Page 243 DMA transfer, the IDMA request register is reset to "0" and an interrupt request for the interrupt factor that enabled IDMA invoking is generated. After an initial reset, this register is set to "0" (Interrupt is requested). EPSON S1C33L03 FUNCTION PART B-II-5-19...
  • Page 244 IDMA request bit can be reset by the hardware between the read and the write, so be careful when using this method. After an initial reset, IDMAONLY is set to "1" (set-only method). EPSON B-II-5-20 S1C33L03 FUNCTION PART...
  • Page 245 Write "1": SIO Ch.3 receive error Write "0": FP2 input Read: Valid Set to "1" to use the SIO Ch.3 receive error interrupt. Set to "0" to use the FP2 input interrupt. At power-on, this bit is set to "0". EPSON S1C33L03 FUNCTION PART B-II-5-21...
  • Page 246 Write "1": 8-bit timer 5 underflow Write "0": FP7 input Read: Valid Set to "1" to use the 8-bit timer 5 underflow interrupt. Set to "0" to use the FP7 input interrupt. At power-on, this bit is set to "0". EPSON B-II-5-22 S1C33L03 FUNCTION PART...
  • Page 247 Write "0": TM16 Ch.3 compare B Read: Valid Set to "1" to use the SIO Ch.2 receive error interrupt. Set to "0" to use the TM16 Ch.3 compare B interrupt. At power-on, this bit is set to "0". EPSON S1C33L03 FUNCTION PART B-II-5-23...
  • Page 248 Before writing to the TTBR register, set TBRP to "0x59" to remove the write protection. Then when data is written to the most significant byte (0x48137) of the TTBR, the register once again becomes write-protected. After an initial reset, TBRP is set to "0x0" (write protected). EPSON B-II-5-24 S1C33L03 FUNCTION PART...

  • Page 249: Programming Notes

    (5) To prevent another interrupt from being generated for the same factor again after generation of an interrupt, be sure to reset the interrupt factor flag before enabling interrupts and setting the PSR again or executing the reti instruction. EPSON S1C33L03 FUNCTION PART B-II-5-25...
  • Page 250 II CORE BLOCK: ITC (Interrupt Controller) THIS PAGE IS BLANK. EPSON B-II-5-26 S1C33L03 FUNCTION PART...

  • Page 251: Clg (Clock Generator)

    CPU and turn off the high-speed (OSC3) oscillation circuit in order to reduce current consumption. In addition, when SLEEP mode is set, the high-speed (OSC3) oscillation circuit is turned off, greatly reducing current consumption (no internal units except for the clock timer need to be operated). EPSON S1C33L03 FUNCTION PART B-II-6-1...

  • Page 252: I/O Pins Of Clock Generator

    Note: When using the PLL, the oscillation frequency range changes according to the PLL setting. See Table 6.2. For details on oscillation characteristics and the external clock input characteristics, refer to "Electrical Characteristics". EPSON B-II-6-2 S1C33L03 FUNCTION PART...

  • Page 253: Pll

    (for 3.3-V crystal resonator, this time is 10 ms max.). To prevent the device from operating erratically, do not use the clock until its oscillation has stabilized. The high-speed (OSC3) oscillation circuit turns off when the CPU is set in SLEEP mode. EPSON S1C33L03 FUNCTION PART B-II-6-3...

  • Page 254: Setting And Switching Over The Cpu Operating Clock

    3. Switch over the CPU operating clock (by writing "1" to CLKCHG). Note: The operating clock switchover by CLKCHG is effective only when both oscillation circuits are on and the power-control register protection flag is set to "0b10010110". EPSON B-II-6-4 S1C33L03 FUNCTION PART...

  • Page 255: Power-Control Register Protection Flag

    Note: The function for waiting until the high-speed (OSC3) oscillation is stabilized by 8T1ON is effective only when SLEEP mode is exited. Writing to 8T1ON is effective only when the power-control register protection flag is set to "0b10010110". EPSON S1C33L03 FUNCTION PART B-II-6-5...

  • Page 256: I/O Memory Of Clock Generator

    Writing to SOSC3 is allowed only when CLGP[7:0] is set to "0b10010110". Note also that if the CPU is operating using the OSC3 clock, writing "0" to SOSC3 is ignored and the oscillation is not turned off. At initial reset, SOSC3 is set to "1" (OSC3 oscillation turned on). EPSON B-II-6-6 S1C33L03 FUNCTION PART...
  • Page 257 Writing to HLT2OP is allowed only when CLGP[7:0] is set to "0b10010110". At initial reset, HLT2OP is set to "0" (basic mode). The following shows the operating status in HALT mode (basic mode and HALT2 mode) and SLEEP mode. EPSON S1C33L03 FUNCTION PART B-II-6-7...
  • Page 258 This clearing of write protection is effective for only one writing, so the bits are cleared to "0b00000000" by one writing. Therefore, CLGP[7:0] must be set each time the protected address is written to. At initial reset, CLGP is set to "0b00000000" (write-protected). EPSON B-II-6-8 S1C33L03 FUNCTION PART...

  • Page 259: Programming Notes

    Therefore, a restart is effected when the input level from a port is active by level. Consequently, the system design should assume that a restart by means of port input from the SLEEP state or HALT2 state is performed by level. EPSON S1C33L03 FUNCTION PART B-II-6-9...
  • Page 260 If the peripheral circuit clock frequency is equal to or higher than the base clock frequency, the peripheral circuit does not operate normally. EPSON B-II-6-10 S1C33L03 FUNCTION PART...

  • Page 261: Dbg (Debug Unit)

    S1C33 Family) can be connected to these pins. Leave these pins open if the S5U1C33000H is not connected. For connecting the S5U1C33000H, refer to the "S5U1C33000H Manual (S1C33 Family In-Circuit Debugger)". Furthermore, the pin status is fixed as shown in the above table after a user reset. EPSON S1C33L03 FUNCTION PART B-II-7-1...
  • Page 262 II CORE BLOCK: DBG (Debug Unit) THIS PAGE IS BLANK. EPSON B-II-7-2 S1C33L03 FUNCTION PART...

  • Page 263: Peripheral Block

    S1C33L03 FUNCTION PART III PERIPHERAL BLOCK...

  • Page 265: Introduction

    C33_ADC C33_PERI Pads Intro (A/D converter) (Prescaler, 8-bit timer, 16-bit timer, Clock timer, Serial interface, Ports) C33 Analog Block C33 Peripheral Block Figure 1.1 Peripheral Block Note: Internal ROM is not provided in the S1C33L03. EPSON S1C33L03 FUNCTION PART B-III-1-1...
  • Page 266 III PERIPHERAL BLOCK: INTRODUCTION THIS PAGE IS BLANK. EPSON B-III-1-2 S1C33L03 FUNCTION PART...

  • Page 267: Prescaler

    (DRAM refresh), A/D converter, serial interface, and ports) that use the prescaler input clock (the source clock for prescaler) can be turned off, stop the prescaler by writing "0" to PSCON. This helps to reduce current consumption. EPSON S1C33L03 FUNCTION PART B-III-2-1...

  • Page 268: Selecting Division Ratio And Output Control For Prescaler

    The clock output is controlled by the P8TONx bit even if P8TPCKx is set to "1". When P8TPCKx is "0", the divided clock that is selected by P8TSx[2:0] will be output to the 8-bit timer x. At initial reset, P8TPCKx is set to "0" and P8TSx[2:0] becomes effective. EPSON B-III-2-2 S1C33L03 FUNCTION PART...

  • Page 269: I/O Memory Of Prescaler

    P16TON2 16-bit timer 2 clock control 1 On 0 Off register P16TS22 16-bit timer 2 P16TS2[2:0] Division ratio : selected by P16TS21 clock division ratio selection /4096 Prescaler clock select P16TS20 /1024 register (0x40181) /256 EPSON S1C33L03 FUNCTION PART B-III-2-3...
  • Page 270 1 On 0 Off P8TS02 8-bit timer 0 P8TS0[2:0] Division ratio : selected by P8TS01 clock division ratio selection /256 Prescaler clock select P8TS00 /128 register (0x40181) 8-bit timer 0 can generate the DRAM refresh clock. EPSON B-III-2-4 S1C33L03 FUNCTION PART...
  • Page 271 (e.g., 16-bit programmable timers, 8-bit programmable timers, A/D converter, serial interface, and ports). Therefore, do not turn off the prescaler when these peripheral circuits are used. At initial reset, PSCON is set to "1" (On). EPSON S1C33L03 FUNCTION PART B-III-2-5...
  • Page 272 The desired division ratio can be selected from among the eight ratios shown on the I/O map. Note that the division ratio differs for each peripheral circuit. These bits can also be read out. At initial reset, all of these bits are set to "0b000" (highest frequency available). EPSON B-III-2-6 S1C33L03 FUNCTION PART...
  • Page 273 The clock output is controlled by the P8TONx bit even if P8TPCKx is set to "1". When "0" is written, the divided clock that is selected by P8TSx[2:0] will be output to the 8-bit timer x. At initial reset, P8TPCKx is set to "0" (divided clock). EPSON S1C33L03 FUNCTION PART B-III-2-7...

  • Page 274: Programming Notes

    (B) stops. When some these circuits of the above (A) need to be used, turn off all other unnecessary circuits and stop the clock supply from the prescaler to those circuits. EPSON B-III-2-8...

  • Page 275: 8-Bit Programmable Timers

    8-bit programmable timer. At cold start, the register is set to input mode. At hot start, the register retains its status from prior to the reset. EPSON S1C33L03 FUNCTION PART...

  • Page 276: Uses Of 8-Bit Programmable Timers

    CPU can be started up by that underflow signal. To use this function, write "0" to the oscillation circuit control bit 8T1ON (D2) / Clock option register (0x40190) to enable the oscillation stabilization waiting function. EPSON B-III-3-2 S1C33L03 FUNCTION PART...
  • Page 277 5 by dividing it by 2 is supplied to the serial interface as its operating clock. This enables the transfer rate of the serial interface to be programmed. To use this function, write "0" to the serial interface control bit SSCK3 (D2) / Serial I/F Ch.3 control register (0x401F8) to select the internal clock. EPSON S1C33L03 FUNCTION PART B-III-3-3...

  • Page 278: Control And Operation Of 8-Bit Programmable Timer

    "Prescaler".) • Do not use a clock that is faster than the CPU operating clock as the 8-bit programmable timer. • When setting an input clock, make sure the 8-bit programmable timer is turned off. EPSON B-III-3-4 S1C33L03 FUNCTION PART...
  • Page 279 When the terminal count is reached and the counter underflows, the initial value is reloaded from the reload data register into the counter. EPSON S1C33L03 FUNCTION PART B-III-3-5...
  • Page 280 Timer 3 data: PTD3[7:0] (D[7:0]) / 8-bit timer 3 counter data register (0x4016E) Timer 4 data: PTD4[7:0] (D[7:0]) / 8-bit timer 4 counter data register (0x40176) Timer 5 data: PTD5[7:0] (D[7:0]) / 8-bit timer 5 counter data register (0x4017A) EPSON B-III-3-6 S1C33L03 FUNCTION PART...

  • Page 281: Control Of Clock Output

    3) The timer output is left as "0" when the timer output is turned on after setting the input clock and timer initial value. 4) When an underflow occurs after starting the timer, the port outputs a pulse with the same width as the 8-bit timer input clock pulse (prescaler's output). EPSON S1C33L03 FUNCTION PART B-III-3-7...

  • Page 282: 8-Bit Programmable Timer Interrupts And Dma

    The registers can also be set so as not to generate an interrupt, with only a DMA transfer performed. For details on IDMA transfers and interrupt control upon completion of IDMA transfer, refer to "IDMA (Intelligent DMA)". EPSON B-III-3-8 S1C33L03 FUNCTION PART...
  • Page 283 Timer 0 underflow interrupt: 0x0C000D0 Timer 1 underflow interrupt: 0x0C000D4 Timer 2 underflow interrupt: 0x0C000D8 Timer 3 underflow interrupt: 0x0C000DC The base address of the trap table can be changed using the TTBR register (0x48134 to 0x48137). B-III EPSON S1C33L03 FUNCTION PART B-III-3-9...

  • Page 284: I/O Memory Of 8-Bit Programmable Timers

    RLD20 = LSB RLD24 RLD23 RLD22 RLD21 RLD20 8-bit timer 2 004016A PTD27 8-bit timer 2 counter data 0 to 255 counter data PTD26 PTD27 = MSB register PTD25 PTD20 = LSB PTD24 PTD23 PTD22 PTD21 PTD20 EPSON B-III-3-10 S1C33L03 FUNCTION PART...
  • Page 285 I/F Ch.0 PSIO02 Serial interface Ch.0 0 to 7 interrupt PSIO01 interrupt level priority register PSIO00 – reserved – – – 0 when being read. P8TM2 8-bit timer 0–3 interrupt level 0 to 7 P8TM1 P8TM0 EPSON S1C33L03 FUNCTION PART B-III-3-11...
  • Page 286 0 P21, etc. CFEX1 P10, P11, P13 port extended 1 DST0 0 P10, etc. function DST1 P11, etc. DPC0 P13, etc. CFEX0 P12, P14 port extended function 1 DST2 0 P12, etc. DCLK P14, etc. EPSON B-III-3-12 S1C33L03 FUNCTION PART...
  • Page 287 There are two cases in which the reload data is loaded into the counter: when data is preset after "1" is written to PSETx, or when data is automatically reloaded upon counter underflow. At initial reset, RLD is not initialized. EPSON S1C33L03 FUNCTION PART B-III-3-13...
  • Page 288 While in a STOP state, the counter retains its count until it is preset with reload data or placed in a RUN state. When the state is changed from STOP to RUN, the counter can restart counting beginning with the retained count. At initial reset, PTRUNx is set to "0" (STOP). EPSON B-III-3-14 S1C33L03 FUNCTION PART...
  • Page 289 When written using the reset-only method (default) Write "1": Interrupt factor flag is reset Write "0": Invalid When written using the read/write method Write "1": Interrupt flag is set Write "0": Interrupt flag is reset EPSON S1C33L03 FUNCTION PART B-III-3-15...
  • Page 290 If the bit is set to "0", normal interrupt processing is performed and IDMA is not invoked. For details on IDMA, refer to "IDMA (Intelligent DMA)". At initial reset, R8TUx is set to "0" (interrupt request). EPSON B-III-3-16 S1C33L03 FUNCTION PART...

  • Page 291: Programming Notes

    (6) To prevent another interrupt from being generated again by the same factor after an interrupt has occurred, be sure to reset the interrupt factor flag (F8TUx) before setting the PSR again or executing the reti instruction. EPSON S1C33L03 FUNCTION PART...
  • Page 292 III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS THIS PAGE IS BLANK. EPSON B-III-3-18 S1C33L03 FUNCTION PART...