16-Bit Timer Interrupt - Epson S1C17704 Technical Manual

11 16-BIT TIMERS (T16)

11.8 16-bit Timer Interrupt

The 16-bit timer outputs an interrupt request signal to the interrupt controller (ITC) when the counter underflows.
To generate a timer underflow interrupt, set up the interrupt level and enable the interrupt using the ITC registers.
ITC registers for timer interrupts
Table 11.8.1 shows the control registers of the ITC provided for each timer channel.
Timer channel
Ch.0
Ch.1
Ch.2
ITC_IFLG register (0x4300)
ITC_EN register (0x4302)
ITC_ILV0 register (0x430e)
ITC_ILV1 register (0x4310)
When an underflow occurs in the timer, the corresponding interrupt flag is set to 1.
If the interrupt enable bit corresponding to that interrupt flag has been set to 1, the ITC sends an interrupt
request to the S1C17 Core. To disable the timer interrupt, set the interrupt enable bit to 0.
The interrupt flag is always set to 1 by the timer underflow pulse, regardless of how the interrupt enable bit is
set (even when set to 0).
The interrupt level setup bits set the interrupt level (0 to 7) of the timer interrupt. If the same interrupt level is
set, timer Ch.0 has highest priority and timer Ch.2 has lowest priority.
An interrupt request to the S1C17 Core is accepted only when all the conditions described below are met.
• The interrupt enable bit is set to 1.
• The IE (Interrupt Enable) bit of the PSR (Processor Status Register) in the S1C17 Core is set to 1.
• The timer interrupt has a higher interrupt level than the value that is set in the IL field of the PSR.
• No other cause of interrupt having higher priority, such as NMI, has occurred.
For details on these interrupt control registers, as well as the device operation when an interrupt has occurred,
see Chapter 6, "Interrupt Controller (ITC)."
Interrupt vectors
The following shows the vector numbers and vector addresses for the timer interrupt:
11-10
Table 11.8.1 ITC Registers
Interrupt flag
IIFT1 (D9/ITC_IFLG)
IIFT2 (D10/ITC_IFLG)
IIFT3 (D11/ITC_IFLG)
Table 11.8.2 Timer Interrupt Vectors
Timer channel Vector number
Timer Ch.0
Timer Ch.1
Timer Ch.2
Interrupt enable bit
IIEN1 (D9/ITC_EN)
IIEN2 (D10/ITC_EN)
IIEN3 (D11/ITC_EN)
Vector address
13 (0x0d) 0x8034
14 (0x0e) 0x8038
15 (0x0f) 0x803c
EPSON
Interrupt level setup bits
IILV1[2:0] (D[10:8]/ITC_ILV0)
IILV2[2:0] (D[2:0]/ITC_ILV1)
IILV3[2:0] (D[10:8]/ITC_ILV1)
S1C17704 TECHNICAL MANUAL