Clock Timer Run/Stop Control - Epson S1C17704 Technical Manual

15 CLOCK TIMER (CT)

15.4 Clock Timer Run/Stop Control

Before starting the clock timer, set up the conditions as shown below.
(1) Set up the interrupt level and enable the clock timer interrupt if the interrupt is used. See Section 15.5.
(2) Reset the timer. See Section 15.3.
The clock timer provides CTRUN (D0/CT_CTL register) to run and stop the counter.
∗ CTRUN: Clock Timer Run/Stop Control Bit in the Clock Timer Control (CT_CTL) Register (D0/0x5000)
The clock timer starts counting when 1 is written to CTRUN. The clock input is disabled and the timer stops
counting when 0 is written to CTRUN. This control does not affect the counter data (CT_CNT register). Even when
the timer has stopped counting, the counter retains its count so that the timer can start counting again from that
point.
When both CTRUN and CTRST are set to 1 at the same time, the timer starts counting after resetting the counter.
While the timer is running, a cause of interrupt occurs at the falling edge of the 32 Hz, 8 Hz, 2 Hz, and 1 Hz
signals. If the interrupt has been enabled, an interrupt request is sent to the interrupt controller (ITC).
OSC1•1/128 256 Hz
CTCNT0 128 Hz
CTCNT1 64 Hz
CTCNT2 32 Hz
CTCNT3 16 Hz
CTCNT4 8 Hz
CTCNT5 4 Hz
CTCNT6 2 Hz
CTCNT7 1 Hz
32 Hz interrupt
8 Hz interrupt
2 Hz interrupt
1 Hz interrupt
Note: The clock timer is actually made to Run/Stop in sync with the falling edge of the 256 Hz signal
after writing to CTRUN. Therefore, when 0 is written to the CTRUN, the timer stops after the
counter is incremented. The CTRUN maintains 1 for reading until the timer actually enters Stop
status.
Figure 15.4.2 shows the timer operation at start/stop.
15-4
Figure 15.4.1 Timing Chart of Clock Timer
256 Hz
CTRUN(RD)
CTRUN(WR)
CT_CNT register 0x57
Figure 15.4.2 Clock Timer Start/Stop Operation
0x58 0x59 0x5a 0x5b
EPSON
0x5c
S1C17704 TECHNICAL MANUAL