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16 STOPWATCH TIMER (SWT)
0x5023: Stopwatch Timer Interrupt Flag Register (SWT_IFLG)
Register name Address
Bit
Stopwatch
0x5023
D7–3 –
Timer Interrupt
(8 bits)
D2
Flag Register
D1
(SWT_IFLG)
D0
This register indicates the interrupt cause occurrence status by the stopwatch timer 100 Hz, 10 Hz, and 1 Hz
signals. When a stopwatch timer interrupt occurs, read the interrupt flag in this register to determine the cause of
interrupt that has occurred (or frequency).
The SIF∗ bits are the interrupt flags that correspond to 100 Hz, 10 Hz, and 1 Hz interrupts respectively, and are
set to 1 at the falling edge of the signals if the corresponding SIE∗ bit (SWT_IMSK register) has been set to 1.
At this time, the stopwatch timer interrupt request signal is output to the ITC. The interrupt request signal sets the
stopwatch timer interrupt flag in the ITC to 1 and an interrupt occurs if other interrupt conditions meet the ITC and
S1C17 Core settings.
The settings shown below are required to manage the cause-of-interrupt occurrence status using this register.
1. Set the stopwatch timer interrupt trigger mode in the ITC to level trigger.
2. After an interrupt occurs, reset the interrupt flag of the SWT module in the interrupt handler routine (this also
resets the interrupt flag in the ITC).
The SIF∗ flags are reset by writing 1.
Note: To avoid occurrence of unnecessary interrupts, be sure to reset the SIF∗ flags before the
stopwatch timer interrupt is enabled using SIE∗.
D[7:3]
Reserved
D2
SIF1: 1 Hz Interrupt Flag
This is the interrupt flag to indicate the 1 Hz interrupt cause occurrence status.
1 (R):
Cause of interrupt has occurred
0 (R):
No cause of interrupt has occurred (default)
1 (W):
Flag is reset
0 (W):
Has no effect
SIF1 is set to 1 at the falling edge of the 1 Hz signal only when SIE1 (D2/SWT_IMSK register) has
been set to 1.
D1
SIF10: 10 Hz Interrupt Flag
This is the interrupt flag to indicate the 10 Hz interrupt cause occurrence status.
1 (R):
Cause of interrupt has occurred
0 (R):
No cause of interrupt has occurred (default)
1 (W):
Flag is reset
0 (W):
Has no effect
SIF10 is set to 1 at the falling edge of the 10 Hz signal only when SIE10 (D1/SWT_IMSK register) has
been set to 1.
D0
SIF100: 100 Hz Interrupt Flag
This is the interrupt flag to indicate the 100 Hz interrupt cause occurrence status.
1 (R):
Cause of interrupt has occurred
0 (R):
No cause of interrupt has occurred (default)
1 (W):
Flag is reset
0 (W):
Has no effect
SIF100 is set to 1 at the falling edge of the 100 Hz signal only when SIE100 (D0/SWT_IMSK register)
has been set to 1.
16-12
Name
Function
reserved
SIF1
1 Hz interrupt flag
SIF10
10 Hz interrupt flag
SIF100
100 Hz interrupt flag
Setting
–
1 Cause of
0 Cause of
interrupt
occurred
EPSON
Init. R/W
Remarks
–
–
0 when being read.
0
R/W Reset by writing 1.
interrupt not
0
R/W
occurred
0
R/W
S1C17704 TECHNICAL MANUAL
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