Epson S1C17704 Technical Manual page 254

18 UART
Selecting the IrDA receive detection clock
Select a prescaler output clock within the range from PCLK•1/1 to PCLK•1/128 as the input pulse detection
clock using the IRCLK[2:0] bits (D[6:4]/UART_EXP register).
∗ IRCLK[2:0]: IrDA Receive Detection Clock Select Bits in the UART Expansion (UART_EXP) Register
(D[6:4]/0x4105)
This clock must be faster than the transfer clock sclk supplied from the 8-bit timer or input from the SCLK pin.
The demodulator regards a low pulse of which the width is longer than two cycles of the IrDA receive detection
clock as a valid low pulse and converts it to a 16 sclk cycles width of low pulse. Select an appropriate prescaler
output clock that can detect a minimum 1.41 µs width of an input pulse.
Controlling serial data transfer
The control method to transmit/receive data in IrDA mode is the same as that of the normal interface. See
previous sections for details on how to set and control the data formats, data transfers, and interrupts.
18-12
Table 18.8.1 Selecting the IrDA Receive Detection Clock
IRCLK[2:0]
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
EPSON
Prescaler output clock
PCLK•1/128
PCLK•1/64
PCLK•1/32
PCLK•1/16
PCLK•1/8
PCLK•1/4
PCLK•1/2
PCLK•1/1
(Default: 0x0)
S1C17704 TECHNICAL MANUAL