Epson S1C17704 Technical Manual page 414

APPENDIX C POWER SAVING
The peripheral modules listed below operate with a clock other than PCLK except for accessing their control
registers. Therefore, PCLK is not required after the control registers are set once and the module starts
operating.
- Clock timer
- Stopwatch timer
- Watchdog timer
- 8-bit OSC1 timer
- LCD driver
While PCLK is stopped, no maskable interrupt can be generated. Maskable interrupts are put on hold until
PCLK supply is resumed.
Table C.1.1 lists the clock control conditions and how to suspend/resume the CPU operation.
Current
OSC1
consumption
↑
Stop
Low
Oscillating
(System clock)
Oscillating
(System clock)
Oscillating
(System clock)
Oscillating
Oscillating
High
Oscillating
↓
Clearing HALT and SLEEP modes (CPU resuming methods)
1. Resuming by a port
The CPU resumes operating by occurrence of a cause of I/O port interrupt or a debug interrupt (issuing an
ICD forced break). If the interrupt controller or the IE flag in the CPU has been set to disable the I/O port
interrupt, the CPU does not accept the interrupt request and starts executing the instructions that follow the
halt or slp instruction. When the interrupt has been enabled and PCLK was activated before the halt or
slp instruction is executed, the CPU executes the interrupt handler. When PCLK was stopped before the
halt or slp instruction is executed, the interrupt is put on hold until PCLK supply is resumed even if the
interrupt has been enabled.
2. Resuming by an OSC1 peripheral
The CPU resumes operating by occurrence of a cause of clock timer, stopwatch timer, watchdog timer, or
8-bit OSC1 timer interrupt. If the interrupt controller or the IE flag in the CPU has been set to disable these
interrupts, the CPU does not accept the interrupt request and starts executing the instructions that follow the
halt instruction. When the interrupt has been enabled and PCLK was activated before the halt instruction
is executed, the CPU executes the interrupt handler. When PCLK was stopped before the halt instruction is
executed, the interrupt is put on hold until PCLK supply is resumed even if the interrupt has been enabled.
3. Resuming by a PCLK peripheral
The CPU resumes operating by occurrence of a cause of interrupt in a PCLK peripheral whose interrupt is
enabled by the interrupt controller. If the IE flag in the CPU has been set to 0, the CPU does not accept the
interrupt request and starts executing the instructions that follow the halt instruction. If the IE flag has been
set to 1, the CPU executes the interrupt handler.
AP-32
Table C.1.1 List of Clock Control Conditions
CPU
OSC3
(CCLK)
Stop Stop
Stop Stop
Stop Stop
Stop Run (1/1)
Oscillating
Stop
(System clock)
Oscillating
Run (low gear)
(System clock)
Oscillating
Run (1/1)
(System clock)
PCLK OSC1
peripherals peripherals
Stop Stop
Stop Run
Run Run
Run Run
Run Run
Run Run
Run Run
EPSON
CPU suspending CPU resuming
method method
slp instruction
1
halt instruction
1, 2
halt instruction
1, 2, 3
halt instruction
1, 2, 3
S1C17704 TECHNICAL MANUAL