Epson ARM720T Core cpu Manuals

Table of Contents

• • 5

    Table of Contents
  • 15

    About This Document

• 19

  1 Introduction

  • 21

    About the ARM720T Processor
  • 22

    Figure 1-1 720T Block Diagram
  • 23

    Figure 1-2 ARM720T Processor Functional Signals
  • 25

    Coprocessors
  • 25

    About the Instruction Set
  • 26

    Table 1-1 Key to Tables
  • 27

    Figure 1-3 ARM Instruction Set Formats
  • 28

    Table 1-2 ARM Instruction Summary
  • 30

    Table 1-3 Addressing Mode 2
  • 31

    Table 1-4 Addressing Mode 2 (Privileged)
  • 31

    Table 1-6 Addressing Mode 4 (Load)
  • 32

    Table 1-7 Addressing Mode 4 (Store)
  • 32

    Table 1-9 Operand 2
  • 32

    Table 1-10 Fields
  • 33

    Table 1-11 Condition Fields
  • 34

    Figure 1-4 Thumb Instruction Set Formats
  • 35

    Table 1-12 Thumb Instruction Summary
  • 38

    Silicon Revisions

• 39

  2 Programmer's Model

  • 41

    Processor Operating States
  • 42

    Memory Formats
  • 42

    Figure 2-1 Big-endian Addresses of Bytes With Words
  • 43

    Instruction Length
  • 43

    Data Types
  • 43

    Figure 2-2 Little-endian Addresses of Bytes With Words
  • 44

    Operating Modes
  • 44

    Registers
  • 44

    Table 2-1 ARM720T Modes of Operation
  • 45

    Figure 2-3 Register Organization in ARM State
  • 46

    Figure 2-4 Register Organization in Thumb State
  • 47

    Figure 2-5 Mapping of Thumb State Registers Onto ARM State Registers
  • 48

    Program Status Registers
  • 48

    Figure 2-6 Program Status Register Format
  • 49

    Table 2-2 PSR Mode Bit Values
  • 50

    Exceptions
  • 51

    Table 2-3 Exception Entry and Exit
  • 53

    Table 2-4 Exception Vector Addresses
  • 55

    Relocation of Low Virtual Addresses By the FCSE PID
  • 56

    Reset
  • 57

    Implementation-defined Behavior of Instructions

• 59

  3 Configuration

  • 61

    About Configuration
  • 62

    Internal Coprocessor Instructions
  • 62

    Figure 3-1 MRC and MCR Bit Pattern
  • 63

    Registers
  • 63

    Figure 3-2 ID Register Read Format
  • 63

    Figure 3-3 ID Register Write Format
  • 63

    Table 3-1 Cache and MMU Control Register
  • 64

    Figure 3-4 Control Register Read Format
  • 64

    Figure 3-5 Control Register Write Format
  • 65

    Figure 3-6 Translation Table Base Register Format
  • 66

    Figure 3-7 Domain Access Control Register Format
  • 66

    Figure 3-8 Fault Status Register Format
  • 67

    Figure 3-9 Fault Address Register Format
  • 67

    Table 3-2 Cache Operation
  • 67

    Table 3-3 TLB Operations
  • 68

    Figure 3-10 FCSCE PID Register Format
  • 68

    Figure 3-11 PROCID Register Format

• 71

  4 Instruction and Data Cache

  • 73

    About the Instruction and Data Cache
  • 74

    IDC Validity
  • 74

    IDC Enable, Disable, and Reset

• 75

  5 Write Buffer

  • 77

    About the Write Buffer
  • 78

    Write Buffer Operation

• 79

  6 The Bus Interface

  • 81

    About the Bus Interface
  • 82

    Figure 6-1 Simple AHB Transfer
  • 83

    Bus Interface Signals
  • 83

    The Bus Interface
  • 84

    Figure 6-2 AHB Bus Master Interface
  • 85

    Transfer Types
  • 85

    Figure 6-3 Simple Memory Cycle
  • 85

    Table 6-1 Transfer Type Encoding
  • 86

    Figure 6-4 Transfer Type Examples
  • 87

    Address and Control Signals
  • 87

    Table 6-2 Transfer Size Encodings
  • 88

    Table 6-3 Burst Type Encodings
  • 88

    Table 6-4 Protection Control Encodings
  • 89

    Slave Transfer Response Signals
  • 90

    Data Buses
  • 90

    Table 6-5 Response Encodings
  • 91

    Table 6-6 Active Byte Lanes for a 32-Bit Little-endian Data Bus
  • 92

    Arbitration
  • 92

    Table 6-7 Active Byte Lanes for a 32-Bit Big-endian Data Bus
  • 93

    Bus Clocking
  • 93

    ARM720T CORE CPU MANUAL EPSON I
    • 93

      Reset

• 95

  7 Memory Management Unit

  • 97

    About the MMU
    • 98

      Access Permissions and Domains
    • 98

      Translated Entries
  • 99

    MMU Program-accessible Registers
  • 99

    Table 7-1 CP15 Register Functions
  • 99

    Memory Management Unit
  • 100

    Address Translation
    • 100

      Figure 7-1 Translation Table Base Register
    • 101

      Figure 7-2 Translating Page Tables
    • 102

      Figure 7-3 Accessing Translation Table Level One Descriptors
    • 102

      Figure 7-4 Level One Descriptor
    • 103

      Table 7-2 Level One Descriptor Bits
    • 103

      Table 7-3 Interpreting Level One Descriptor Bits [1:0]
    • 104

      Figure 7-5 Section Descriptor
    • 104

      Figure 7-6 Coarse Page Table Descriptor
    • 104

      Table 7-4 Section Descriptor Bits
    • 105

      Figure 7-7 Fine Page Table Descriptor
    • 105

      Table 7-5 Coarse Page Table Descriptor Bits
    • 105

      Table 7-6 Fine Page Table Descriptor Bits
    • 106

      Figure 7-8 Section Translation
    • 106

      Figure 7-9 Level Two Descriptor
    • 107

      Table 7-7 Level Two Descriptor Bits
    • 107

      Table 7-8 Interpreting Page Table Entry Bits [1:0]
  • 108

    Figure 7-10 Large Page Translation From a Coarse Page Table
  • 109

    Figure 7-11 Small Page Translation From a Coarse Page Table
  • 110

    Figure 7-12 Tiny Page Translation From a Fine Page Table
  • 111

    MMU Faults and CPU Aborts
  • 112

    Fault Address and Fault Status Registers
  • 112

    Table 7-9 Priority Encoding of Fault Status
  • 113

    Domain Access Control
  • 113

    Figure 7-13 Domain Access Control Register Format
  • 113

    Table 7-10 Interpreting Access Control Bits in Domain Access Control Register
  • 114

    Table 7-11 Interpreting Access Permission (AP) Bits
  • 115

    Fault Checking Sequence
  • 115

    Figure 7-14 Sequence for Checking Faults
  • 117

    External Aborts
  • 117

    Interaction of the MMU and Cache

• 119

  8 Coprocessor Interface

  • 121

    About Coprocessors
  • 122

    Table 8-1 Coprocessor Availability
  • 123

    Coprocessor Interface Signals
  • 124

    Pipeline-following Signals
  • 125

    Coprocessor Interface Handshaking
  • 125

    Table 8-2 Handshaking Signals
  • 126

    Figure 8-1 Coprocessor Busy-wait Sequence
  • 127

    Figure 8-2 Coprocessor Register Transfer Sequence
  • 127

    Figure 8-3 Coprocessor Data Operation Sequence
  • 128

    Figure 8-4 Coprocessor Load Sequence
  • 129

    Connecting Coprocessors
  • 129

    Figure 8-5 Example Coprocessor Connections
  • 129

    Table 8-3 Handshake Signal Connections
  • 130

    Not Using an External Coprocessor
  • 130

    STC Operations
  • 130

    Undefined Instructions
  • 130

    Privileged Instructions
  • 130

    Table 8-4 CPnTRANS Signal Meanings

• 131

  9 Debugging Your System

  • 134

    About Debugging Your System
  • 134

    Figure 9-1 Typical Debug System
  • 135

    Controlling Debugging
  • 135

    Figure 9-2 ARM720T Processor Block Diagram
  • 136

    Debug Modes
  • 137

    Entry Into Debug State
  • 137

    Figure 9-3 Debug State Entry
  • 140

    Figure 9-4 Clock Synchronization
  • 141

    Debug Interface
  • 141

    ARM720T Core Clock Domains
  • 142

    The EmbeddedICE-RT Macrocell
  • 142

    Figure 9-5 the ARM720T Core, TAP Controller, and EmbeddedICE-RT Macrocell
  • 143

    Disabling EmbeddedICE-RT
  • 144

    EmbeddedICE-RT Register Map
  • 144

    Monitor Mode Debugging
  • 144

    Table 9-1 Function and Mapping of EmbeddedICE-RT Registers
  • 146

    The Debug Communications Channel
  • 146

    Figure 9-6 Domain Access Control Register
  • 147

    Table 9-2 Domain Access Control Register Bit Assignments
  • 149

    Scan Chains and the JTAG Interface
    • 149

      Figure 9-7 ARM720T Processor Scan Chain Arrangements
    • 150

      Table 9-3 Instruction Encodings for Scan Chain 15
  • 151

    The TAP Controller
  • 151

    Figure 9-8 Test Access Port Controller State Transitions
  • 152

    Public JTAG Instructions
  • 152

    Table 9-4 Public Instructions
  • 154

    Test Data Registers
  • 154

    Figure 9-9 ID Code Register Format
  • 155

    Table 9-5 Scan Chain Number Allocation
  • 157

    Scan Timing
  • 157

    Figure 9-10 Scan Timing
  • 157

    Table 9-6 Scan Chain 1 Cells
  • 158

    Examining the Core and the System in Debug State
  • 161

    Exit From Debug State
  • 161

    Figure 9-11 Debug Exit Sequence
  • 162

    The Program Counter During Debug
  • 164

    Priorities and Exceptions
  • 164

    Table 9-7 Determining the Cause of Entry to Debug State
  • 165

    Watchpoint Unit Registers
    • 166

      Figure 9-12 EmbeddedICE-RT Block Diagram
    • 167

      Figure 9-13 Watchpoint Control Value, and Mask Format
    • 167

      Table 9-8 SIZE[1:0] Signal Encoding
  • 168

    Programming Breakpoints
  • 170

    Programming Watchpoints
  • 170

    Abort Status Register
  • 170

    Figure 9-14 Debug Abort Status Register
  • 171

    Debug Control Register
    • 171

      Figure 9-15 Debug Control Register Format
    • 171

      Table 9-9 Debug Control Register Bit Assignments
    • 172

      Table 9-10 Interrupt Signal Control
  • 173

    Debug Status Register
    • 173

      Figure 9-16 Debug Status Register Format
    • 173

      Table 9-11 Debug Status Register Bit Assignments
    • 174

      Figure 9-17 Debug Control and Status Register Structure
  • 175

    Coupling Breakpoints and Watchpoints
  • 176

    EmbeddedICE-RT Timing

• 177

  10 ETM Interface

  • 179

    About the ETM Interface
  • 179

    Enabling and Disabling the ETM7 Interface
  • 180

    Connections Between the ETM7 Macrocell and the ARM720T Processor
  • 181

    Clocks and Resets
  • 181

    Debug Request Wiring
  • 181

    TAP Interface Wiring

• 183

  11 Test Support

  • 185

    About the ARM720T Test Registers
  • 185

    Figure 11-1 CP15 MRC and MCR Bit Pattern
  • 186

    Automatic Test Pattern Generation (ATPG)
  • 186

    Table 11-1 Summary of ATPG Test Signals
  • 187

    Test State Register
  • 187

    Cache Test Registers and Operations
    • 187

      Table 11-2 Test State Register Operations
    • 188

      Figure 11-2 Rd Format, CAM Read
    • 188

      Figure 11-3 Rd Format, CAM Write
    • 188

      Table 11-3 Summary of CP15 Register C7, C9, and C15 Operations
    • 189

      Figure 11-4 Rd Format, RAM Read
    • 189

      Figure 11-5 Rd Format, RAM Write
    • 189

      Figure 11-6 Rd Format, CAM Match RAM Read
    • 189

      Figure 11-7 Data Format, CAM Read
    • 189

      Figure 11-8 Data Format, RAM Read
    • 190

      Figure 11-9 Data Format, CAM Match RAM Read
    • 190

      Figure 11-10 Rd Format, Write Cache Victim and Lockdown Base
    • 190

      Figure 11-11 Rd Format, Write Cache Victim
    • 190

      Table 11-4 Write Cache Victim and Lockdown Operations
  • 192

    MMU Test Registers and Operations
    • 193

      Table 11-5 CAM, RAM1, and RAM2 Register C15 Operations
    • 193

      Table 11-6 Register C2, C3, C5, C6, C8, C10, and C15 Operations
    • 194

      Figure 11-12 Rd Format, CAM Write and Data Format, CAM Read
    • 194

      Figure 11-13 Rd Format, RAM1 Write
    • 194

      Table 11-7 CAM Memory Region Size
    • 195

      Figure 11-14 Data Format, RAM1 Read
    • 195

      Figure 11-15 Rd Format, RAM2 Write and Data Format, RAM2 Read
    • 195

      Table 11-8 Access Permission Bit Setting
    • 195

      Table 11-9 Miss and Fault Encoding
    • 196

      Figure 11-16 Rd Format, Write TLB Lockdown
    • 196

      Table 11-10 RAM2 Memory Region Size
  • 201

    A Signal Descriptions
    • 201

      AMBA Interface Signals
    • 202

      Coprocessor Interface Signals
    • 202

      Table A-2 Coprocessor Interface Signal Descriptions
    • 203

      JTAG and Test Signals
    • 203

      Table A-3 JTAG and Test Signal Descriptions
    • 204

      Debugger Signals
      • 204

        A.4 Debugger Signals
      • 204

        Table A-4 Debugger Signal Descriptions
    • 205

      Embedded Trace Macrocell Interface Signals
    • 205

      Table A-5 ETM Interface Signal Descriptions
    • 207

      ATPG Test Signals
    • 207

      Miscellaneous Signals
      • 207

        A.7 Miscellaneous Signals
      • 207

        Table A-6 ATPG Test Signal Descriptions
      • 207

        Table A-7 Miscellaneous Signal Descriptions