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Epson ARM720T Core cpu Core Cpu Manual

Epson ARM720T Core cpu Core Cpu Manual (224 pages)

Revision 4  
Brand: Epson | Category: Computer Hardware | Size: 1.6 MB
Table of contents
Table Of Contents5................................................................................................................................................................
About This Document15................................................................................................................................................................
Introduction19................................................................................................................................................................
About The Arm720t Processor21................................................................................................................................................................
Figure 1-1 720t Block Diagram22................................................................................................................................................................
Figure 1-2 Arm720t Processor Functional Signals23................................................................................................................................................................
Coprocessors25................................................................................................................................................................
About The Instruction Set25................................................................................................................................................................
Table 1-1 Key To Tables26................................................................................................................................................................
Figure 1-3 Arm Instruction Set Formats27................................................................................................................................................................
Table 1-2 Arm Instruction Summary28................................................................................................................................................................
Table 1-3 Addressing Mode 230................................................................................................................................................................
Table 1-4 Addressing Mode 2 (privileged)31................................................................................................................................................................
Table 1-6 Addressing Mode 4 (load)31................................................................................................................................................................
Table 1-7 Addressing Mode 4 (store)32................................................................................................................................................................
Table 1-9 Operand 232................................................................................................................................................................
Table 1-10 Fields32................................................................................................................................................................
Table 1-11 Condition Fields33................................................................................................................................................................
Figure 1-4 Thumb Instruction Set Formats34................................................................................................................................................................
Table 1-12 Thumb Instruction Summary35................................................................................................................................................................
Silicon Revisions38................................................................................................................................................................
Programmer's Model39................................................................................................................................................................
Processor Operating States41................................................................................................................................................................
Memory Formats42................................................................................................................................................................
Figure 2-1 Big-endian Addresses Of Bytes With Words42................................................................................................................................................................
Instruction Length43................................................................................................................................................................
Data Types43................................................................................................................................................................
Figure 2-2 Little-endian Addresses Of Bytes With Words43................................................................................................................................................................
Operating Modes44................................................................................................................................................................
Registers44................................................................................................................................................................
Table 2-1 Arm720t Modes Of Operation44................................................................................................................................................................
Figure 2-3 Register Organization In Arm State45................................................................................................................................................................
Figure 2-4 Register Organization In Thumb State46................................................................................................................................................................
Figure 2-5 Mapping Of Thumb State Registers Onto Arm State Registers47................................................................................................................................................................
Program Status Registers48................................................................................................................................................................
Figure 2-6 Program Status Register Format48................................................................................................................................................................
Table 2-2 Psr Mode Bit Values49................................................................................................................................................................
Exceptions50................................................................................................................................................................
Table 2-3 Exception Entry And Exit51................................................................................................................................................................
Table 2-4 Exception Vector Addresses53................................................................................................................................................................
Relocation Of Low Virtual Addresses By The Fcse Pid55................................................................................................................................................................
Reset56................................................................................................................................................................
Implementation-defined Behavior Of Instructions57................................................................................................................................................................
Configuration59................................................................................................................................................................
About Configuration61................................................................................................................................................................
Internal Coprocessor Instructions62................................................................................................................................................................
Figure 3-1 Mrc And Mcr Bit Pattern62................................................................................................................................................................
Figure 3-2 Id Register Read Format63................................................................................................................................................................
Figure 3-3 Id Register Write Format63................................................................................................................................................................
Table 3-1 Cache And Mmu Control Register63................................................................................................................................................................
Figure 3-4 Control Register Read Format64................................................................................................................................................................
Figure 3-5 Control Register Write Format64................................................................................................................................................................
Figure 3-6 Translation Table Base Register Format65................................................................................................................................................................
Figure 3-7 Domain Access Control Register Format66................................................................................................................................................................
Figure 3-8 Fault Status Register Format66................................................................................................................................................................
Figure 3-9 Fault Address Register Format67................................................................................................................................................................
Table 3-2 Cache Operation67................................................................................................................................................................
Table 3-3 Tlb Operations67................................................................................................................................................................
Figure 3-10 Fcsce Pid Register Format68................................................................................................................................................................
Figure 3-11 Procid Register Format68................................................................................................................................................................
Instruction And Data Cache71................................................................................................................................................................
About The Instruction And Data Cache73................................................................................................................................................................
Idc Validity74................................................................................................................................................................
Idc Enable, Disable, And Reset74................................................................................................................................................................
Write Buffer75................................................................................................................................................................
About The Write Buffer77................................................................................................................................................................
Write Buffer Operation78................................................................................................................................................................
The Bus Interface79................................................................................................................................................................
About The Bus Interface81................................................................................................................................................................
Figure 6-1 Simple Ahb Transfer82................................................................................................................................................................
Bus Interface Signals83................................................................................................................................................................
Figure 6-2 Ahb Bus Master Interface84................................................................................................................................................................
Transfer Types85................................................................................................................................................................
Figure 6-3 Simple Memory Cycle85................................................................................................................................................................
Table 6-1 Transfer Type Encoding85................................................................................................................................................................
Figure 6-4 Transfer Type Examples86................................................................................................................................................................
Address And Control Signals87................................................................................................................................................................
Table 6-2 Transfer Size Encodings87................................................................................................................................................................
Table 6-3 Burst Type Encodings88................................................................................................................................................................
Table 6-4 Protection Control Encodings88................................................................................................................................................................
Slave Transfer Response Signals89................................................................................................................................................................
Data Buses90................................................................................................................................................................
Table 6-5 Response Encodings90................................................................................................................................................................
Table 6-6 Active Byte Lanes For A 32-bit Little-endian Data Bus91................................................................................................................................................................
Arbitration92................................................................................................................................................................
Table 6-7 Active Byte Lanes For A 32-bit Big-endian Data Bus92................................................................................................................................................................
Bus Clocking93................................................................................................................................................................
Arm720t Core Cpu Manual Epson I93................................................................................................................................................................
Memory Management Unit95................................................................................................................................................................
About The Mmu97................................................................................................................................................................
Access Permissions And Domains98................................................................................................................................................................
Translated Entries98................................................................................................................................................................
Mmu Program-accessible Registers99................................................................................................................................................................
Table 7-1 Cp15 Register Functions99................................................................................................................................................................
Address Translation100................................................................................................................................................................
Figure 7-1 Translation Table Base Register100................................................................................................................................................................
Figure 7-2 Translating Page Tables101................................................................................................................................................................
Figure 7-3 Accessing Translation Table Level One Descriptors102................................................................................................................................................................
Figure 7-4 Level One Descriptor102................................................................................................................................................................
Table 7-2 Level One Descriptor Bits103................................................................................................................................................................
Table 7-3 Interpreting Level One Descriptor Bits [1:0]103................................................................................................................................................................
Figure 7-5 Section Descriptor104................................................................................................................................................................
Figure 7-6 Coarse Page Table Descriptor104................................................................................................................................................................
Table 7-4 Section Descriptor Bits104................................................................................................................................................................
Figure 7-7 Fine Page Table Descriptor105................................................................................................................................................................
Table 7-5 Coarse Page Table Descriptor Bits105................................................................................................................................................................
Table 7-6 Fine Page Table Descriptor Bits105................................................................................................................................................................
Figure 7-8 Section Translation106................................................................................................................................................................
Figure 7-9 Level Two Descriptor106................................................................................................................................................................
Table 7-7 Level Two Descriptor Bits107................................................................................................................................................................
Table 7-8 Interpreting Page Table Entry Bits [1:0]107................................................................................................................................................................
Figure 7-10 Large Page Translation From A Coarse Page Table108................................................................................................................................................................
Figure 7-11 Small Page Translation From A Coarse Page Table109................................................................................................................................................................
Figure 7-12 Tiny Page Translation From A Fine Page Table110................................................................................................................................................................
Mmu Faults And Cpu Aborts111................................................................................................................................................................
Fault Address And Fault Status Registers112................................................................................................................................................................
Table 7-9 Priority Encoding Of Fault Status112................................................................................................................................................................
Domain Access Control113................................................................................................................................................................
Figure 7-13 Domain Access Control Register Format113................................................................................................................................................................
Table 7-10 Interpreting Access Control Bits In Domain Access Control Register113................................................................................................................................................................
Table 7-11 Interpreting Access Permission (ap) Bits114................................................................................................................................................................
Fault Checking Sequence115................................................................................................................................................................
Figure 7-14 Sequence For Checking Faults115................................................................................................................................................................
External Aborts117................................................................................................................................................................
Interaction Of The Mmu And Cache117................................................................................................................................................................
Coprocessor Interface119................................................................................................................................................................
About Coprocessors121................................................................................................................................................................
Table 8-1 Coprocessor Availability122................................................................................................................................................................
Coprocessor Interface Signals123................................................................................................................................................................
Pipeline-following Signals124................................................................................................................................................................
Coprocessor Interface Handshaking125................................................................................................................................................................
Table 8-2 Handshaking Signals125................................................................................................................................................................
Figure 8-1 Coprocessor Busy-wait Sequence126................................................................................................................................................................
Figure 8-2 Coprocessor Register Transfer Sequence127................................................................................................................................................................
Figure 8-3 Coprocessor Data Operation Sequence127................................................................................................................................................................
Figure 8-4 Coprocessor Load Sequence128................................................................................................................................................................
Connecting Coprocessors129................................................................................................................................................................
Figure 8-5 Example Coprocessor Connections129................................................................................................................................................................
Table 8-3 Handshake Signal Connections129................................................................................................................................................................
Not Using An External Coprocessor130................................................................................................................................................................
Stc Operations130................................................................................................................................................................
Undefined Instructions130................................................................................................................................................................
Privileged Instructions130................................................................................................................................................................
Table 8-4 Cpntrans Signal Meanings130................................................................................................................................................................
Debugging Your System131................................................................................................................................................................
About Debugging Your System134................................................................................................................................................................
Figure 9-1 Typical Debug System134................................................................................................................................................................
Controlling Debugging135................................................................................................................................................................
Figure 9-2 Arm720t Processor Block Diagram135................................................................................................................................................................
Debug Modes136................................................................................................................................................................
Entry Into Debug State137................................................................................................................................................................
Figure 9-3 Debug State Entry137................................................................................................................................................................
Figure 9-4 Clock Synchronization140................................................................................................................................................................
Debug Interface141................................................................................................................................................................
Arm720t Core Clock Domains141................................................................................................................................................................
The Embeddedice-rt Macrocell142................................................................................................................................................................
Figure 9-5 The Arm720t Core, Tap Controller, And Embeddedice-rt Macrocell142................................................................................................................................................................
Disabling Embeddedice-rt143................................................................................................................................................................
Embeddedice-rt Register Map144................................................................................................................................................................
Monitor Mode Debugging144................................................................................................................................................................
Table 9-1 Function And Mapping Of Embeddedice-rt Registers144................................................................................................................................................................
The Debug Communications Channel146................................................................................................................................................................
Figure 9-6 Domain Access Control Register146................................................................................................................................................................
Table 9-2 Domain Access Control Register Bit Assignments147................................................................................................................................................................
Scan Chains And The Jtag Interface149................................................................................................................................................................
Figure 9-7 Arm720t Processor Scan Chain Arrangements149................................................................................................................................................................
Table 9-3 Instruction Encodings For Scan Chain 15150................................................................................................................................................................
The Tap Controller151................................................................................................................................................................
Figure 9-8 Test Access Port Controller State Transitions151................................................................................................................................................................
Public Jtag Instructions152................................................................................................................................................................
Table 9-4 Public Instructions152................................................................................................................................................................
Test Data Registers154................................................................................................................................................................
Figure 9-9 Id Code Register Format154................................................................................................................................................................
Table 9-5 Scan Chain Number Allocation155................................................................................................................................................................
Scan Timing157................................................................................................................................................................
Figure 9-10 Scan Timing157................................................................................................................................................................
Table 9-6 Scan Chain 1 Cells157................................................................................................................................................................
Examining The Core And The System In Debug State158................................................................................................................................................................
Exit From Debug State161................................................................................................................................................................
Figure 9-11 Debug Exit Sequence161................................................................................................................................................................
The Program Counter During Debug162................................................................................................................................................................
Priorities And Exceptions164................................................................................................................................................................
Table 9-7 Determining The Cause Of Entry To Debug State164................................................................................................................................................................
Watchpoint Unit Registers165................................................................................................................................................................
Figure 9-12 Embeddedice-rt Block Diagram166................................................................................................................................................................
Figure 9-13 Watchpoint Control Value, And Mask Format167................................................................................................................................................................
Table 9-8 Size[1:0] Signal Encoding167................................................................................................................................................................
Programming Breakpoints168................................................................................................................................................................
Programming Watchpoints170................................................................................................................................................................
Abort Status Register170................................................................................................................................................................
Figure 9-14 Debug Abort Status Register170................................................................................................................................................................
Debug Control Register171................................................................................................................................................................
Figure 9-15 Debug Control Register Format171................................................................................................................................................................
Table 9-9 Debug Control Register Bit Assignments171................................................................................................................................................................
Table 9-10 Interrupt Signal Control172................................................................................................................................................................
Debug Status Register173................................................................................................................................................................
Figure 9-16 Debug Status Register Format173................................................................................................................................................................
Table 9-11 Debug Status Register Bit Assignments173................................................................................................................................................................
Figure 9-17 Debug Control And Status Register Structure174................................................................................................................................................................
Coupling Breakpoints And Watchpoints175................................................................................................................................................................
Embeddedice-rt Timing176................................................................................................................................................................
Etm Interface177................................................................................................................................................................
About The Etm Interface179................................................................................................................................................................
Enabling And Disabling The Etm7 Interface179................................................................................................................................................................
Connections Between The Etm7 Macrocell And The Arm720t Processor180................................................................................................................................................................
Clocks And Resets181................................................................................................................................................................
Debug Request Wiring181................................................................................................................................................................
Tap Interface Wiring181................................................................................................................................................................
Test Support183................................................................................................................................................................
About The Arm720t Test Registers185................................................................................................................................................................
Figure 11-1 Cp15 Mrc And Mcr Bit Pattern185................................................................................................................................................................
Automatic Test Pattern Generation (atpg)186................................................................................................................................................................
Table 11-1 Summary Of Atpg Test Signals186................................................................................................................................................................
Test State Register187................................................................................................................................................................
Cache Test Registers And Operations187................................................................................................................................................................
Table 11-2 Test State Register Operations187................................................................................................................................................................
Figure 11-2 Rd Format, Cam Read188................................................................................................................................................................
Figure 11-3 Rd Format, Cam Write188................................................................................................................................................................
Table 11-3 Summary Of Cp15 Register C7, C9, And C15 Operations188................................................................................................................................................................
Figure 11-4 Rd Format, Ram Read189................................................................................................................................................................
Figure 11-5 Rd Format, Ram Write189................................................................................................................................................................
Figure 11-6 Rd Format, Cam Match Ram Read189................................................................................................................................................................
Figure 11-7 Data Format, Cam Read189................................................................................................................................................................
Figure 11-8 Data Format, Ram Read189................................................................................................................................................................
Figure 11-9 Data Format, Cam Match Ram Read190................................................................................................................................................................
Figure 11-10 Rd Format, Write Cache Victim And Lockdown Base190................................................................................................................................................................
Figure 11-11 Rd Format, Write Cache Victim190................................................................................................................................................................
Table 11-4 Write Cache Victim And Lockdown Operations190................................................................................................................................................................
Mmu Test Registers And Operations192................................................................................................................................................................
Table 11-5 Cam, Ram1, And Ram2 Register C15 Operations193................................................................................................................................................................
Table 11-6 Register C2, C3, C5, C6, C8, C10, And C15 Operations193................................................................................................................................................................
Figure 11-12 Rd Format, Cam Write And Data Format, Cam Read194................................................................................................................................................................
Figure 11-13 Rd Format, Ram1 Write194................................................................................................................................................................
Table 11-7 Cam Memory Region Size194................................................................................................................................................................
Figure 11-14 Data Format, Ram1 Read195................................................................................................................................................................
Figure 11-15 Rd Format, Ram2 Write And Data Format, Ram2 Read195................................................................................................................................................................
Table 11-8 Access Permission Bit Setting195................................................................................................................................................................
Table 11-9 Miss And Fault Encoding195................................................................................................................................................................
Figure 11-16 Rd Format, Write Tlb Lockdown196................................................................................................................................................................
Table 11-10 Ram2 Memory Region Size196................................................................................................................................................................
A Signal Descriptions201................................................................................................................................................................
Amba Interface Signals201................................................................................................................................................................
Table A-2 Coprocessor Interface Signal Descriptions202................................................................................................................................................................
Jtag And Test Signals203................................................................................................................................................................
Table A-3 Jtag And Test Signal Descriptions203................................................................................................................................................................
Debugger Signals204................................................................................................................................................................
A.4 Debugger Signals204................................................................................................................................................................
Table A-4 Debugger Signal Descriptions204................................................................................................................................................................
Embedded Trace Macrocell Interface Signals205................................................................................................................................................................
Table A-5 Etm Interface Signal Descriptions205................................................................................................................................................................
Atpg Test Signals207................................................................................................................................................................
Miscellaneous Signals207................................................................................................................................................................
A.7 Miscellaneous Signals207................................................................................................................................................................
Table A-6 Atpg Test Signal Descriptions207................................................................................................................................................................
Table A-7 Miscellaneous Signal Descriptions207................................................................................................................................................................

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