User Manuals: Epson ARM720T Core cpu ARM Processor

Manuals and User Guides for Epson ARM720T Core cpu ARM Processor. We have 1 Epson ARM720T Core cpu ARM Processor manual available for free PDF download: Core Cpu Manual

Epson ARM720T Core cpu Core Cpu Manual

Epson ARM720T Core cpu Core Cpu Manual (224 pages)

Revision 4 (AMBA AHB Bus Interface Version)

Brand: Epson | Category: Computer Hardware | Size: 1.6 MB

Table of Contents

Table of Contents
5
About this Document
15
1 Introduction

19
2 Programmer's Model

39
3 Configuration

59
4 Instruction and Data Cache

71
5 Write Buffer

75
- About the Write Buffer
  77
- Write Buffer Operation
  78
6 The Bus Interface

79
7 Memory Management Unit

95
8 Coprocessor Interface

119
- About Coprocessors
  121
- Table 8-1 Coprocessor Availability
  122
- Coprocessor Interface Signals
  123
- Pipeline-Following Signals
  124
- Coprocessor Interface Handshaking
  125
- Table 8-2 Handshaking Signals
  125
- Figure 8-1 Coprocessor Busy-Wait Sequence
  126
- Figure 8-2 Coprocessor Register Transfer Sequence
  127
- Figure 8-3 Coprocessor Data Operation Sequence
  127
- Figure 8-4 Coprocessor Load Sequence
  128
- Connecting Coprocessors
  129
- Figure 8-5 Example Coprocessor Connections
  129
- Table 8-3 Handshake Signal Connections
  129
- Not Using an External Coprocessor
  130
- STC Operations
  130
- Undefined Instructions
  130
- Privileged Instructions
  130
- Table 8-4 Cpntrans Signal Meanings
  130
9 Debugging Your System

131
- About Debugging Your System
  134
- Figure 9-1 Typical Debug System
  134
- Controlling Debugging
  135
- Figure 9-2 ARM720T Processor Block Diagram
  135
- Debug Modes
  136
- Entry into Debug State
  137
- Figure 9-3 Debug State Entry
  137
- Figure 9-4 Clock Synchronization
  140
- Debug Interface
  141
- ARM720T Core Clock Domains
  141
- The Embeddedice-RT Macrocell
  142
- Figure 9-5 the ARM720T Core, TAP Controller, and Embeddedice-RT Macrocell
  142
- Disabling Embeddedice-RT
  143
- Embeddedice-RT Register Map
  144
- Monitor Mode Debugging
  144
- Table 9-1 Function and Mapping of Embeddedice-RT Registers
  144
- The Debug Communications Channel
  146
- Figure 9-6 Domain Access Control Register
  146
- Table 9-2 Domain Access Control Register Bit Assignments
  147
- Scan Chains and the JTAG Interface
  149
  - Figure 9-7 ARM720T Processor Scan Chain Arrangements
    149
  - Table 9-3 Instruction Encodings for Scan Chain 15
    150
- The TAP Controller
  151
- Figure 9-8 Test Access Port Controller State Transitions
  151
- Public JTAG Instructions
  152
- Table 9-4 Public Instructions
  152
- Test Data Registers
  154
- Figure 9-9 ID Code Register Format
  154
- Table 9-5 Scan Chain Number Allocation
  155
- Scan Timing
  157
- Figure 9-10 Scan Timing
  157
- Table 9-6 Scan Chain 1 Cells
  157
- Examining the Core and the System in Debug State
  158
- Exit from Debug State
  161
- Figure 9-11 Debug Exit Sequence
  161
- The Program Counter During Debug
  162
- Priorities and Exceptions
  164
- Table 9-7 Determining the Cause of Entry to Debug State
  164
- Watchpoint Unit Registers
  165
- Programming Breakpoints
  168
- Programming Watchpoints
  170
- Abort Status Register
  170
- Figure 9-14 Debug Abort Status Register
  170
- Debug Control Register
  171
- Debug Status Register
  173
- Coupling Breakpoints and Watchpoints
  175
- Embeddedice-RT Timing
  176
10 ETM Interface

177
- About the ETM Interface
  179
- Enabling and Disabling the ETM7 Interface
  179
- Connections between the ETM7 Macrocell and the ARM720T Processor
  180
- Clocks and Resets
  181
- Debug Request Wiring
  181
- TAP Interface Wiring
  181
11 Test Support

183
A Signal Descriptions

201
- AMBA Interface Signals
  201
- Coprocessor Interface Signals
  202
- Table A-2 Coprocessor Interface Signal Descriptions
  202
- JTAG and Test Signals
  203
- Table A-3 JTAG and Test Signal Descriptions
  203
- Debugger Signals
  204
  - A.4 Debugger Signals
    204
  - Table A-4 Debugger Signal Descriptions
    204
- Embedded Trace Macrocell Interface Signals
  205
- Table A-5 ETM Interface Signal Descriptions
  205
- ATPG Test Signals
  207
- Miscellaneous Signals
  207

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