Epson S1C17704 Technical Manual page 227

EIFT2 is set to 1 at the falling edge of the 100/10/1 Hz signal whose interrupt is enabled. If EIEN2 has been set
to 1, the ITC sends an interrupt request to the S1C17 Core. To disable the stopwatch timer interrupt, set EIEN2
to 0. EIFT2 is always set to 1 by the interrupt signal sent from the SWT module, regardless of how EIEN2 is set
(even when set to 0).
EILV2[2:0] sets the interrupt level (0 to 7) of the stopwatch timer interrupt.
An interrupt request to the S1C17 Core is accepted only when all the conditions described below are met.
• The interrupt enable bit is set to 1.
• The IE (Interrupt Enable) bit of the PSR (Processor Status Register) in the S1C17 Core is set to 1.
• The stopwatch timer interrupt has a higher interrupt level than the value that is set in the IL field of the PSR.
• No other cause of interrupt having higher priority, such as NMI, has occurred.
For details on these interrupt control registers, as well as the device operation when an interrupt has occurred,
see Chapter 6, "Interrupt Controller (ITC)."
Note: The settings shown below are required to manage the cause-of-interrupt occurrence status using
the interrupt flags in the SWT module.
1. Set the stopwatch timer interrupt trigger mode in the ITC to level trigger.
2. After an interrupt occurs, reset the SIF∗ interrupt flag of the SWT module in the interrupt
handler routine (this also resets the interrupt flag in the ITC).
Interrupt vector
The following shows the vector number and vector address for the stopwatch timer interrupt:
Vector number: 6 (0x06)
Vector address: 0x8018
S1C17704 TECHNICAL MANUAL
EPSON
16 STOPWATCH TIMER (SWT)
16-7