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Epson S1C33 Series Core Manual

Epson S1C33 Series Core Manual

Cmos 32-bit single chip microcomputer
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CMOS 32 - BIT SINGLE CHIP MICROCOMPUTER
S1C33 Family C33 PE
Core Manual

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Summary of Contents for Epson S1C33 Series

  • Page 1 CMOS 32 - BIT SINGLE CHIP MICROCOMPUTER S1C33 Family C33 PE Core Manual...
  • Page 2 No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not...
  • Page 3 Configuration of product number Devices 33209 00E1 Packing specifications 00 : Besides tape & reel 0A : TCP BL 2 directions 0B : Tape & reel BACK 0C : TCP BR 2 directions 0D : TCP BT 2 directions 0E : TCP BD 2 directions 0F : Tape &...

  • Page 5: Table Of Contents

    4 Address Map ......................... 17 5 Instruction Set ......................18 5.1 S1C33-Series-Compatible Instructions ................18 5.2 Function Extended Instructions..................20 5.3 Instructions Added to the C33 PE Core ................21 5.4 Instructions Removed ...................... 21 EPSON S1C33 FAMILY C33 PE CORE MANUAL...
  • Page 6 6.3.7 Software Exceptions ..................55 6.3.8 Maskable External Interrupts ................55 6.3.9 Undefined Instruction Exception ................ 56 6.3.10 ext Exception....................56 6.4 Power-Down Mode ......................57 6.5 Debug Circuit ........................58 6.6 Coprocessor Interface ...................... 59 EPSON S1C33 FAMILY C33 PE CORE MANUAL...
  • Page 7 %rd, [%rb]........................... 111 ld.ub %rd, [%rb]+..........................112 ld.ub %rd, [%sp + imm6]........................113 ld.uh %rd, %rs ............................. 114 ld.uh %rd, [%rb]........................... 115 ld.uh %rd, [%rb]+..........................116 ld.uh %rd, [%sp + imm6]........................117 EPSON S1C33 FAMILY C33 PE CORE MANUAL...
  • Page 8 %sp, imm10 ..........................164 swap %rd, %rs ............................. 165 swaph %rd, %rs ........................... 166 xor %rd, %rs ............................167 xor %rd, sign6............................168 Appendix Instruction Code List (in Order of Codes) ..........169 EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 9: Summary

    1 SUMMARY 1 Summary The C33 PE is a RISC type processor in the S1C33 series of Seiko Epson 32-bit microcomputers. The C33 PE (Processor Element) Core is a Seiko Epson original 32-bit RISC-type core processor for the S1C33 Family microprocessors. Based on the C33 STD Core CPU features, some useful C33 ADV Core functions/ instructions were added and some of the infrequently used ones in general applications are removed to realize a high cost-performance core unit with high processing speed.

  • Page 10: Summary Of Added/Changed Functions Of The C33 Pe

    Correction of the result of signed step division, 2 div3s Multiply-accumulate operation Scan bits for 0 scan0 Scan bits for 1 scan1 Mirroring mirror These functions can be realized using the software library provided or by other means. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 11: Registers

    2. Pipeline The 3-stage pipeline in the C33 STD Core CPU has been modified to a 2-stage pipeline in the C33 PE Core (consisting of fetch/decode and execute/access/write back). EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 12: Registers

    PC. During cold reset, TTBR is initialized to “0xC00000,” so that the address written at the address “0xC00000” is the start address of the program. Effective address Figure 2.2.1 Program Counter (PC) EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 13: Processor Status Register (Psr)

    0 when the result of the add or subtract operation is within the range of values representable by a signed 32-bit integer. This flag is also reset to 0 by executing a logical operation instruction. EPSON S1C33 FAMILY C33 PE CORE MANUAL...
  • Page 14 N flag. If the operation being executed is step division, the sign bit of the division is set in the N flag, which affects the execution of the division. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 15: Stack Pointer (Sp)

    Next, the content of the register specified in the push instruction is stored at the address pointed to by the SP. rs → [SP] Example: pushn 0xFFFFFFFF 0xFFFFFFFF SP = SP - 12 0x00000000 0x00000000 Figure 2.4.2.1 SP and Stack (1) EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 16: Sp Operation During Execution Of Pop-Related Instructions

    SP operation by the ret instruction (1) [SP] → PC (2) SP = SP + 4 0xFFFFFFFF 0xFFFFFFFF SP = SP + 4 PC[31:0] PC[31:0] 0x00000000 0x00000000 Figure 2.4.4.2 SP and Stack (4) EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 17: Sp Operation When An Interrupt Or Exception Occurs

    SP operation when the reti instruction is executed (1) [SP + 4] → PC (2) [SP] → PSR (3) SP = SP + 8 0xFFFFFFFF 0xFFFFFFFF SP = SP + 8 0x00000000 0x00000000 Figure 2.4.5.2 SP and Stack (6) EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 18: Trap Table Base Register (Ttbr)

    The Debug Base Register (hereinafter referred to as the “DBBR”) is a 32-bit register that contains the base address of a memory area used for debugging. The DBBR is a read-only register which, in the C33 PE Core, is fixed to 0x00060000. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 19: Register Notation And Register Numbers

    The relationship between the general-purpose registers and the register numbers is listed in the table below. Table 2.9.1.1 General-Purpose Registers General-purpose register Register number Register notation %r10 %r11 %r12 %r13 %r14 %r15 EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 20: Special Registers

    Register number Register notation %psr %alr %ahr TTBR * %ttbr IDIR * %idir DBBR * %dbbr The new registers added to the C33 PE Core are marked with * in the above table. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 21: Data Formats

    Bits 31–8 in the destination register are zero-extended. 3.2 Signed 8-Bit Transfer (Register → Register) Example: ld.b %rd,%rs Byte 24 23 16 15 Byte Figure 3.2.1 Signed 8-Bit Transfer (Register → Register) Bits 31–8 in the destination register are sign-extended. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 22: Unsigned 8-Bit Transfer (Memory → Register)

    Figure 3.5.1 8-Bit Transfer (Register → Memory) 3.6 Unsigned 16-Bit Transfer (Register → Register) Example: ld.uh %rd,%rs 16 15 Halfword 16 15 Halfword Figure 3.6.1 Unsigned 16-Bit Transfer (Register → Register) Bits 31–16 in the destination register are zero-extended. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 23: Signed 16-Bit Transfer (Register → Register)

    Bits 31–16 in the destination register are sign-extended. 3.10 16-Bit Transfer (Register → Memory) Example: ld.h [%rb],%rs Byte 1 Byte 0 0x∗∗∗∗∗∗∗1 Byte 1 [%rb] 0x∗∗∗∗∗∗∗0 Byte 0 Figure 3.10.1 16-Bit Transfer (Register → Memory) EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 24: 32-Bit Transfer (Register → Register)

    Example: ld.w [%rb],%rs 16 15 Byte 3 Byte 2 Byte 1 Byte 0 0x∗∗∗∗∗∗11 Byte 3 0x∗∗∗∗∗∗10 Byte 2 0x∗∗∗∗∗∗01 Byte 1 [%rb] 0x∗∗∗∗∗∗00 Byte 0 Figure 3.13.1 32-Bit Transfer (Register → Memory) EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 25: Address Map

    0x402E0–0x402FF, 0x4812D (byte), 0x48134 (word), 0x60000–0x7FFFF These areas and addresses are reserved for debugging functions. Do not allocate these addresses to memories and I/O devices. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 26: Instruction Set

    Core CPU are deleted. As the C33 PE Core is object-code compatible with the C33 STD Core CPU, software assets can be transported from the S1C33 series to the C33 PE model easily, with minimal modifications required. All of the instruction codes are fixed to 16 bits in length which, combined with pipelined processing, allows most important instructions to be executed in one cycle.
  • Page 27 Unsigned immediate (numerals indicating bit length) imm2,imm4,imm3, However, numerals in shift instructions indicate the number of bits imm5,imm6,imm10, shifted, while those in bit manipulation indicate bit positions. imm13 Signed immediate (numerals indicating bit length) sign6,sign8 EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 28: Function Extended Instructions

    (Bits 0–31 rotated as specified by immediate) Data transfer Special register (word) The number of special registers ld.w %rd,%ss → general-purpose register that can be used to load data General-purpose register (word) has been increased. %sd,%rs → special register EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 29: Instructions Added To The C33 Pe Core

    %rd,%rs Multiply-accumulate operation 16 bits × 16 bits + 64 bits → 64 bits Search for bits whose value = 0 scan0 %rd,%rs Search for bits whose value = 1 scan1 %rd,%rs EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 30: Addressing Modes (Without Ext Extension)

    5.5 Addressing Modes (without ext extension) The instruction set of the C33 PE Core, as with the S1C33 series, has six discrete addressing modes, as described below. The processor determines the addressing mode according to the operand in each instruction before it accesses data.

  • Page 31: Register Indirect Addressing

    Word transfer (ld.w): This addressing mode is specified by enclosing the register name in brackets “[],” which is then suffixed by “+.” The register name is actually written as [%r0]+, [%r1]+, ... or [%r15]+. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 32: Register Indirect Addressing With Displacement

    Example: PC + 0 The program branches to the PC + 8 address when the jrne branch jrne 0x04 condition holds true. (PC + 0) + 0x04 ∗ 2 → PC + 8 PC + 8 EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 33: Addressing Modes With Ext

    The most significant bit “S” in imm13 that has been extended by the ext instruction is the sign, with which bits 31–19 are extended to become signed 19-bit data. The most significant bit in sign6 is handled as the MSB data of 6-bit data, and not as the sign. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 34: Extension Of Register Indirect Addressing

    During address calculation, imm26 is zero-extended to 32-bit quantity. Example: ext imm13 (1) imm13 (2) ld.uh %rd,[%rb] Memory address pointer 26 25 13 12 Immediate imm13 (1) imm13 (2) EPSON S1C33 FAMILY C33 PE CORE MANUAL...
  • Page 35 (1) imm13 (2) imm6 [5:1] Halfword transfer imm13 (1) imm13 (2) imm6 [5:2] Word transfer The extended data and the sp are added to comprise the source or destination address of transfer. EPSON S1C33 FAMILY C33 PE CORE MANUAL...
  • Page 36 %rd,%rs If not extended, rd = rd + rs When extended by two ext instructions, rd = rs + imm26 Data 26 25 13 12 Immediate imm13 (1) imm13 (2) Data + imm26 EPSON S1C33 FAMILY C33 PE CORE MANUAL...
  • Page 37 (2) sign8 Current address New address The most significant bit “S” in the immediate that has been extended by ext instructions is the sign. Bits 2–0 in the first ext instruction are unused. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 38: Exception Handling For Ext Instructions

    (For two ext instructions, control returns to the first ext.) EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 39: Data Transfer Instructions

    24 23 16 15 Byte data Signed halfword data transfer 16 15 Halfword data Extended with the sign in bit 15 of the halfword data Unsigned halfword data transfer 16 15 Halfword data EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 40: Logical Operation Instructions

    32-bit data in a specified general-purpose register or signed immediate data (6, 19, or 32 bits). Differences from the C33 STD Core CPU When a logical operation is performed, the V flag (bit 2) in the PSR is cleared. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 41: Arithmetic Operation Instructions

    The cmp instruction compares two operands, and may alter a flag, depending on the comparison result. Basically, it is used to set conditions for conditional jump instructions. If an immediate smaller than word in size is specified as the source, it is sign-extended when comparison is performed. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 42: Multiply Instructions

    AHR and ALR, with the 32 high-order bits stored in the former and the 32 low-order bits stored in the latter. The C33 PE Core executes 16-bit × 16-bit multiplication in five cycle and 32-bit × 32-bit multiplication in seven cycles. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 43: Shift And Rotate Instructions

    10011 00100 10100 00101 10101 00110 10110 00111 10111 01000 11000 01001 11001 01010 11010 01011 11011 01100 11100 01101 11101 01110 11110 01111 11111 Bits 5–31 in the rs are not used. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 44: Bit Manipulation Instructions

    Therefore, if the addresses to be manipulated have any I/O control bits mapped whose function is enabled by a bit write operation, use of these instructions requires caution. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 45: Push And Pop Instructions

    The stack pointer is updated before the register data is pushed onto the stack. SP = SP - 4, rs → [SP] Figure 5.13.1 Successive Push of General-Purpose Registers EPSON S1C33 FAMILY C33 PE CORE MANUAL...
  • Page 46 Before execution of push low address low address Figure 5.13.5 Single Push of a General-Purpose Register Before execution of pop After execution of pop low address low address Figure 5.13.6 Single Pop of a General-Purpose Register EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 47: Branch And Delayed Branch Instructions

    The imm13 specified by the ext instruction is extended as the 13 high-order bits of sign22. sign22 S S S imm13 sign8 Current address Branch destination address The range of addresses to which jumped is (PC - 2,097,152) to (PC + 2,097,150). EPSON S1C33 FAMILY C33 PE CORE MANUAL...
  • Page 48 A < B jrult A ≤ B Unsigned, Less or Equal Z | C jrule Equal A = B jreq A ≠ B Not Equal jrne Comparison of A:B made when “cmp A,B” EPSON S1C33 FAMILY C33 PE CORE MANUAL...
  • Page 49 Since these instructions are basically provided for the debug firmware, please do not use them in application programs. For details on the functionality of these instructions, refer to Section 6.5, “Debug Circuit.” Differences from the C33 STD Core CPU Register indirect relative branch instructions have been added. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 50: Delayed Branch Instructions

    %rd,imm5 swap %rd,%rs swaph %rd,%rs ld.c %rd,imm4 ld.c imm4,%rs Note: Unless the above conditions are satisfied, the instruction may operate unstably. Therefore, it is prohibited to use such instructions as delayed slot instructions. EPSON S1C33 FAMILY C33 PE CORE MANUAL...
  • Page 51 Note: The ld.w %rd,%pc instruction must be executed as a delayed slot instruction. If it does not follow a delayed branch instruction, the PC value that is loaded into the rd register may not be the next instruction address to the ld.w instruction. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 52: System Control Instructions

    Places the processor in HALT mode halt Places the processor in SLEEP mode For details on HALT and SLEEP modes, refer to Section 6.4, “Power-Down Mode,” and the Technical Manual for each S1C33 model. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 53: Swap Instructions

    Byte 2 Byte 1 Byte 0 Byte 2 Byte 3 Byte 0 Byte 1 24 23 16 15 Differences from the C33 STD Core CPU The swaph instruction has been added. swaph %rd,%rs EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 54: Other Instructions

    Sets the PSR bit specified by imm5[2:0] (0–4) to 1 psrset imm5 Clears the PSR bit specified by imm5[2:0] (0–4) to 0 psrclr imm5 The contents of PSR are not altered when the imm5 is 5 or more. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 55: Functions

    The processor is placed in HALT or SLEEP mode to reduce power consumption by executing the halt or slp instruction in the software (see Section 6.4). Normally the processor can be taken out of HALT or SLEEP mode by NMI or an external interrupt as well as initial reset. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 56: Program Execution

    Note: The pipelined operation shown above uses the internal memory. If external memory or low-speed external devices are used, one or more wait cycles may be inserted depending on the devices used, with the E stage kept waiting. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 57: Execution Cycles And Flags

    3–4 (∗3) – – – – ret.d ↔ ↔ ↔ ↔ PSR change reti – – – – retd – – – – IE = 0 imm2 – – – – IE no change EPSON S1C33 FAMILY C33 PE CORE MANUAL...
  • Page 58 – – %rd,%rs ↔ ↔ – – %rd,imm5 ↔ ↔ – – %rd,%rs ↔ ↔ – – %rd,imm5 Data transfer – – – – ld.w %rd,%ss 1–3 (∗5) – – – – %sd,%rs EPSON S1C33 FAMILY C33 PE CORE MANUAL...
  • Page 59 ∗4 +1 cycle when ext is used ∗5 Three cycles when %psr is specified ∗6 Two cycles when %alr is specified or three cycles when %ahr is specified In the C33 PE Core, no interlock cycle is generated. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 60: Interrupts And Exceptions

    0x00060008 PC save area 0x0006000C R0 save area During debug exception handling, neither other exceptions nor multiple debug exceptions are accepted. They are kept pending until the debug exception handling currently underway finishes. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 61: Vector Table

    As only bits 31–10 in the TTBR are referenced, the vector table must be located in a 1K-byte boundary RAM area. TTBR[31:10] Vector code (10 bits) Vector code is generated by the processor. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 62: Exception Handling

    Nor does this exception occur in the instructions that involve branching of the program flow (e.g., call %rb or jp %rb), as the least significant bit of the PC is always fixed to 0. The same applies to the vector for exception handling. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 63: Nmi

    In the interrupt handler routine, the reti instruction should be executed at the end of processing. In the reti instruction, the saved data is restored from the stack in order of the PC and PSR, and the processing returns to the suspended instruction. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 64: Undefined Instruction Exception

    Address TTBR + 8 is used to store the ext exception vector. When an instruction, which does not support the extension in the ext instruction, follows an ext, the ext instruction will be executed as a nop instruction. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 65: Power-Down Mode

    When the interrupt has been disabled, the processor restarts the program from the instruction next to halt or slp after the processor is taken out of HALT or SLEEP mode. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 66: Debug Circuit

    When returning from the exception by the retd instruction, the processor restores the saved data in order of the R0 and the PC. Neither hardware interrupts nor NMI interrupts are accepted during a debug exception. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 67: Coprocessor Interface

    Transfer C, V, Z, and N flags from the coprocessor ld.cf The concrete commands and status of the coprocessor vary with each coprocessor connected to the chip. Please refer to the user’s manual for the coprocessor used. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 68: Details Of Instructions

    Indicates that the bit is not changed by instruction execution ↔ Indicates that the bit is set (= 1) or reset (= 0) by instruction execution Indicates that the bit is reset (= 0) by instruction execution EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 69: Adc %Rd, %Rs

    ; r0 = r0 + r1 + C (2) Addition of 64-bit data data 1 = {r2, r1}, data2 = {r4, r3}, result = {r2, r1} %r1,%r3 ; Addition of the low-order word %r2,%r4 ; Addition of the high-order word EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 70: Add %Rd, %Rs

    “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Example (1) add %r0,%r0 ; r0 = r0 + r0 (2) ext 0x1fff %r1,%r2 ; r1 = r2 + 0x3fff EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 71: Add %Rd, Imm6

    “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Example (1) add %r0,0x3f ; r0 = r0 + 0x3f (2) ext 0x1fff 0x1fff %r1,0x3f ; r1 = r1 + 0xffffffff EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 72: Add %Sp, Imm10

    32 bits prior to the operation. (2) Delayed instruction This instruction may be executed as a delayed instruction by writing it directly after a branch instruction with the “d” bit. Example %sp,0x100 ; sp = sp + 0x400 EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 73: And %Rd, %Rs

    “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Example (1) and %r0,%r0 ; r0 = r0 & r0 (2) ext 0x1fff %r1,%r2 ; r1 = r2 & 0x00003fff EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 74: And %Rd, Sign6

    “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Example (1) and %r0,0x3e ; r0 = r0 & 0xfffffffe (2) ext 0x7ff %r1,0x3f ; r1 = r1 & 0x0001ffff EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 75: Bclr [%Rb], Imm3

    ; to the R0 register. bclr [%r0],0x0 ; Clears Bit 0 of data in the specified ; address. (2) ext bclr [%r0],0x7 ; Clears Bit 7 of data in the following ; address. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 76: Bnot [%Rb], Imm3

    ; to the R0 register. bnot [%r0],0x0 ; Reverses Bit 0 of data in the specified ; address. (2) ext bnot [%r0],0x7 ; Reverses Bit 7 of data in the following ; address. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 77: Brk

    Furthermore the processor enters the debug mode. The retd instruction must be used for return from the debug-handler routine. This instruction is provided for debug firmware. Do not use it in general programs. Example ; Executes the debug-handler routine EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 78: Bset [%Rb], Imm3

    ; to the R0 register. bset [%r0],0x0 ; Sets Bit 0 of data in the specified ; address. (2) ext bset [%r0],0x7 ; Sets Bit 7 of data in the following ; address. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 79: Btst [%Rb], Imm3

    ; Sets the memory address to be accessed ; to the R0 register. btst [%r0],0x7 ; Tests Bit 7 of data in the specified ; address. jreq POSITIVE ; Jumps if the bit is 0. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 80: Call %Rb / Call.d %Rb

    If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 81: Call Sign8 / Call.d Sign8

    If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 82: Cmp %Rd, %Rs

    (1) cmp %r0,%r1 ; Changes the flags according to the results of ; r0 - r1. (2) ext 0x1fff %r1,%r2 ; Changes the flags according to the results of ; r2 - 0x3fff. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 83: Cmp %Rd, Sign6

    (1) cmp %r0,0x3f ; Changes the flags according to the results of ; r0 - 0x3f. (2) ext 0x1fff 0x1fff %r1,0x3f ; Changes the flags according to the results of ; r1 - 0xffffffff. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 84: Do.c Imm6

    Mode Immediate (unsigned) One cycle Description The command specified by imm6 is issued to the coprocessor. imm6 is output to the dedicated coprocessor address bus. Example do.c 0x1a ; coprocessor execute command 1A EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 85: Ext Imm13

    If the trap handler routine is returned by simply executing the reti instruction, the previous ext instruction is invalidated. Therefore, it is necessary to modify the return address in that case. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 86: Halt

    HALT mode. Refer to the technical manual of each model for details of HALT mode. Example halt ; Sets the processor in HALT mode. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 87: Int Imm2

    The Base is the trap table beginning address set in the TTBR register (default: 0xC00000). The reti instruction should be used for return from the handler routine. Example ; Executes the software exception 2 handler routine. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 88: Jp %Rb / Jp.d %Rb

    If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 89: Jp Sign8 / Jp.d Sign8

    If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 90: Jpr %Rb / Jpr.d %Rb

    If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 91: Jreq Sign8 / Jreq.d Sign8

    If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 92: Jrge Sign8 / Jrge.d Sign8

    If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 93: Jrgt Sign8 / Jrgt.d Sign8

    If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 94: Jrle Sign8 / Jrle.d Sign8

    If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 95: Jrlt Sign8 / Jrlt.d Sign8

    If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 96: Jrne Sign8 / Jrne.d Sign8

    If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 97: Jruge Sign8 / Jruge.d Sign8

    If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 98: Jrugt Sign8 / Jrugt.d Sign8

    If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 99: Jrule Sign8 / Jrule.d Sign8

    If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 100: Jrult Sign8 / Jrult.d Sign8

    If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 101: Ld.b %Rd, %Rs

    32 bits. (2) Delayed instruction This instruction may be executed as a delayed instruction by writing it directly after a branch instruction with the “d” bit. ; r0 ← r1(7:0) sign-extended Example ld.b %r0,%r1 EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 102: Ld.b %Rd, [%Rb]

    26-bit immediate imm26 added comprises the memory address, the byte data in which is transferred to the rd register. The content of the rb register is not altered. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 103: Ld.b %Rd, [%Rb]

    The byte data in the specified memory location is transferred to the rd register after being sign- extended to 32 bits. The rb register contains the memory address to be accessed. Following data transfer, the address in the rb register is incremented by 1. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 104: Ld.b %Rd, [%Sp + Imm6]

    SP with the 32-bit immediate imm32 added comprises the memory address, the byte data in which is transferred to the rd register. Example ; r0 ← [sp + 0x41] sign-extended ld.b %r0,[%sp + 0x1] EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 105: Ld.b [%Rb], %Rs

    26-bit immediate imm26 added. The content of the rb register is not altered. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 106: Ld.b [%Rb]+, %Rs

    The 8 low-order bits of the rs register are transferred to the specified memory location. The rb register contains the memory address to be accessed. Following data transfer, the address in the rb register is incremented by 1. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 107: Ld.b [%Sp + Imm6], %Rs

    SP with the 32-bit immediate imm32 added. Example ; B[sp + 0x41] ← 8 low-order bits of r0 ld.b [%sp + 0x1],%r0 EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 108: Ld.c %Rd, Imm4

    (2) Delayed instruction This instruction may be executed as a delayed instruction by writing it directly after a branch instruction with the “d” bit. ; r1 ← coprocessor reg3 Example ld.c %r1,0x3 EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 109: Ld.c Imm4, %Rs

    (2) Delayed instruction This instruction may be executed as a delayed instruction by writing it directly after a branch instruction with the “d” bit. ; coprocessor reg5 ← r2 Example ld.c 0x5,%r2 EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 110: Ld.cf

    0x01D0 Flag – ↔ ↔ ↔ ↔ Mode – Three cycles Description The C, V, Z, and N flags are transferred from the coprocessor to the PSR(3:0). Example ld.cf ; copy coprocessor flag EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 111: Ld.h %Rd, %Rs

    32 bits. (2) Delayed instruction This instruction may be executed as a delayed instruction by writing it directly after a branch instruction with the “d” bit. ; r0 ← r1(15:0) sign-extended Example ld.h %r0,%r1 EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 112: Ld.h %Rd, [%Rb]

    The content of the rb register is not altered. Caution The rb register and the displacement must specify a halfword boundary address (least significant bit = 0). Specifying an odd address causes an address misaligned exception. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 113: Ld.h %Rd, [%Rb]

    (1) The rb register must specify a halfword boundary address (least significant bit = 0). Specifying an odd address causes an address misaligned exception. (2) If the same register is specified for rd and rb, the incremented address after transferring data is loaded to the rd register. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 114: Ld.h %Rd, [%Sp + Imm6]

    Make sure the imm6 specified here resides on a halfword boundary (least significant bit = 0). Example ; r0 ← [sp + 0x42] sign-extended ld.h %r0,[%sp + 0x2] EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 115: Ld.h [%Rb], %Rs

    26-bit immediate imm26 added. The content of the rb register is not altered. Caution The rb register and the displacement must specify a halfword boundary address (least significant bit = 0). Specifying an odd address causes an address misaligned exception. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 116: Ld.h [%Rb]+, %Rs

    Following data transfer, the address in the rb register is incremented by 2. Caution The rb register and the displacement must specify a halfword boundary address (least significant bit = 0). Specifying an odd address causes an address misaligned exception. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 117: Ld.h [%Sp + Imm6], %Rs

    32-bit immediate imm32 added. Make sure the imm6 specified here resides on a halfword boundary (least significant bit = 0). Example ; H[sp + 0x42] ← 16 low-order bits of r0 ld.h [%sp + 0x2],%r0 EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 118: Ld.ub %Rd, %Rs

    32 bits. (2) Delayed instruction This instruction may be executed as a delayed instruction by writing it directly after a branch instruction with the “d” bit. ; r0 ← r1(7:0) zero-extended Example ld.ub %r0,%r1 EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 119: Ld.ub %Rd, [%Rb]

    26-bit immediate imm26 added comprises the memory address, the byte data in which is transferred to the rd register. The content of the rb register is not altered. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 120: Ld.ub %Rd, [%Rb]

    The byte data in the specified memory location is transferred to the rd register after being zero- extended to 32 bits. The rb register contains the memory address to be accessed. Following data transfer, the address in the rb register is incremented by 1. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 121: Ld.ub %Rd, [%Sp + Imm6]

    SP with the 32-bit immediate imm32 added comprises the memory address, the byte data in which is transferred to the rd register. Example ; r0 ← [sp + 0x41] zero-extended ld.ub %r0,[%sp + 0x1] EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 122: Ld.uh %Rd, %Rs

    32 bits. (2) Delayed instruction This instruction may be executed as a delayed instruction by writing it directly after a branch instruction with the “d” bit. ; r0 ← r1(15:0) zero-extended Example ld.uh %r0,%r1 EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 123: Ld.uh %Rd, [%Rb]

    The content of the rb register is not altered. Caution The rb register and the displacement must specify a halfword boundary address (least significant bit = 0). Specifying an odd address causes an address misaligned exception. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 124: Ld.uh %Rd, [%Rb]

    (1) The rb register must specify a halfword boundary address (least significant bit = 0). Specifying an odd address causes an address misaligned exception. (2) If the same register is specified for rd and rb, the incremented address after transferring data is loaded to the rd register. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 125: Ld.uh %Rd, [%Sp + Imm6]

    Make sure the imm6 specified here resides on a halfword boundary (least significant bit = 0). Example %r0,[%sp + 0x2] ; r0 ← [sp + 0x42] zero-extended ld.uh EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 126: Ld.w %Rd, %Rs

    The content of the rs register (word data) is transferred to the rd register. (2) Delayed instruction This instruction may be executed as a delayed instruction by writing it directly after a branch instruction with the “d” bit. ; r0 ← r1 Example ld.w %r0,%r1 EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 127: Ld.w %Rd, %Ss

    (2) When a special register other than the source registers listed above is specified as %ss, the ld.w instruction will be executed as a nop instruction. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 128: Ld.w %Rd, [%Rb]

    The content of the rb register is not altered. Caution The rb register and the displacement must specify a word boundary address (two least significant bits = 0). Specifying other addresses causes an address misaligned exception. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 129: Ld.w %Rd, [%Rb]

    = 0). Specifying other addresses causes an address misaligned exception. (2) If the same register is specified for rd and rb, the incremented address after transferring data is loaded to the rd register. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 130: Ld.w %Rd, [%Sp + Imm6]

    SP with the 32-bit immediate imm32 added comprises the memory address, the word data in which is transferred to the rd register. Make sure the imm6 specified here resides on a word boundary (two least significant bits = 0). EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 131: Ld.w %Rd, Sign6

    This instruction may be executed as a delayed instruction by writing it directly after a branch instruction with the “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. ; r0 ← 0xffffffff Example ld.w %r0,0x3f EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 132: Ld.w %Sd, %Rs

    ; sp ← r0 Example ld.w %sp,%r0 Caution When a special register other than the destination registers listed above is specified as %sd, the ld.w instruction will be executed as a nop instruction. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 133: Ld.w [%Rb], %Rs

    26-bit immediate imm26 added. The content of the rb register is not altered. Caution The rb register and the displacement must specify a word boundary address (two least significant bits = 0). Specifying an odd address causes an address misaligned exception. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 134: Ld.w [%Rb]+, %Rs

    4. Caution The rb register and the displacement must specify a word boundary address (two least significant bits = 0). Specifying an odd address causes an address misaligned exception. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 135: Ld.w [%Sp + Imm6], %Rs

    SP with the 32-bit immediate imm32 added. Make sure the imm6 specified here resides on a word boundary (two least significant bits = 0). EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 136: Mlt.h %Rd, %Rs

    The 16 low-order bits of the rd register and the 16 low-order bits of the rs register are multiplied together with the signs, and the 32-bit product resulting from the operation is loaded into the ALR register. ; alr ← r0(15:0) × r1(15:0) Example mlt.h %r0,%r1 ; signed multiplication EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 137: Mlt.w %Rd, %Rs

    The content of the rd register and the content of the rs register are multiplied together with the signs, and the 64-bit product resulting from the operation is loaded into the AHR and ALR register pair. ; {ahr,alr} ← r0 × r1 signed multiplication Example mlt.w %r0,%r1 EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 138: Mltu.h %Rd, %Rs

    The 16 low-order bits of the rd register and the 16 low-order bits of the rs register are multiplied together without signs, and the 32-bit product resulting from the operation is loaded into the ALR register. ; alr ← r0(15:0) × r1(15:0) Example mltu.h %r0,%r1 ; unsigned multiplication EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 139: Mltu.w %Rd, %Rs

    The content of the rd register and the content of the rs register are multiplied together without signs, and the 64-bit product resulting from the operation is loaded into the AHR and ALR register pair. %r0,%r1 ; {ahr,alr} ← r0 × r1 unsigned multiplication Example mltu.w EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 140: Nop

    0x0000 Flag – – – – – Mode – One cycle Description The nop instruction just takes 1 cycle and no operation results. The PC is incremented (+2). Example ; Waits 2 cycles EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 141: Not %Rd, %Rs

    (2) Delayed instruction This instruction may be executed as a delayed instruction by writing it directly after a branch instruction with the “d” bit. Example When r1 = 0x55555555 %r0,%r1 ; r0 = 0xAAAAAAAA EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 142: Not %Rd, Sign6

    “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Example (1) not %r0,0x1f ; r0 = 0xffffffe0 (2) ext 0x7ff %r1,0x3f ; r1 = 0xfffe0000 EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 143: Or %Rd, %Rs

    “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Example (1) or %r0,%r0 ; r0 = r0 | r0 (2) ext 0x1fff %r1,%r2 ; r1 = r2 | 0x00003fff EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 144: Or %Rd, Sign6

    “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Example (1) or %r0,0x3e ; r0 = r0 | 0xfffffffe (2) ext 0x7ff %r1,0x3f ; r1 = r1 | 0x0001ffff EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 145: Pop %Rd

    SP to the rd register, and increments the SP by an amount equivalent to 1 word (4 bytes). Stack operation when pop %rd is executed Data Data rd ← Data ; r3 ← W[sp], sp ← sp + 4 Example EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 146: Popn %Rd

    Data 1 Data 1 Data 0 Data 0 r0 ← Data 0 r1 ← Data 1 r2 ← Data 2 r3 ← Data 3 Example popn ; r0, r1, r2, and r3 are restored EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 147: Pops %Sd

    ; registers are restored in order of alr and ahr Caution When a register other than ALR or AHR is specified as the sd register, the pops instruction does not pop data from the stack. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 148: Psrclr Imm5

    0, 1, 2, 3, and 4 representing bits 0 (N), 1 (Z), 2 (V), 3 (C), and 4 (IE), respectively. An imm5 of more than 4 is not effective and does not alter the contents of PSR. ; V ← 0 (V flag cleared) Example psrclr EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 149: Psrset Imm5

    0, 1, 2, 3, and 4 representing bits 0 (N), 1 (Z), 2 (V), 3 (C), and 4 (IE), respectively. An imm5 of more than 4 is not effective and does not alter the contents of PSR. ; V ← 1 (V flag set) Example psrset EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 150: Push %Rs

    The push instruction first decrements the current SP by an amount equivalent to 1 word (4 bytes), and saves the content of the rs register to that address. Stack operation when push %rs is executed rs data ; sp ← sp - 4, W[sp] ← r3 Example push EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 151: Pushn %Rs

    Stack operation when pushn %rs (where %rs = %r3) is executed r3 data r2 data r1 data r0 data Example pushn ; r3, r2, r1, and r0 are saved EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 152: Pushs %Ss

    ; registers are saved in order of ahr and alr Caution When a register other than ALR or AHR is specified as the ss register, the pushs instruction does not save the register data to the stack. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 153: Ret / Ret.d

    If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 154: Retd

    Restore the contents of the R0 and PC that were saved to the debug exception memory space when an debug exception occurred to the respective registers, and return from the debug exception handler routine. Example retd ; Return from a debug exception handler routine EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 155: Reti

    Restore the contents of the PC and PSR that were saved to the stack when an exception or interrupt occurred to the respective registers, and return from the trap handler routine. The SP is incremented by an amount equivalent to 2 words. Example reti ; Return from a trap handler routine EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 156: Rl %Rd, %Rs

    (after execution) (2) Delayed instruction This instruction may be executed as a delayed instruction by writing it directly after a branch instruction with the “d” bit included. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 157: Rl %Rd, Imm5

    (after execution) (2) Delayed instruction This instruction may be executed as a delayed instruction by writing it directly after a branch instruction with the “d” bit included. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 158: Rr %Rd, %Rs

    (after execution) (2) Delayed instruction This instruction may be executed as a delayed instruction by writing it directly after a branch instruction with the “d” bit included. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 159: Rr %Rd, Imm5

    (after execution) (2) Delayed instruction This instruction may be executed as a delayed instruction by writing it directly after a branch instruction with the “d” bit included. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 160: Sbc %Rd, %Rs

    ; r0 = r0 - r1 - C (2) Subtraction of 64-bit data data 1 = {r2, r1}, data2 = {r4, r3}, result = {r2, r1} %r1,%r3 ; Subtraction of the low-order word %r2,%r4 ; Subtraction of the high-order word EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 161: Sla %Rd, %Rs

    (after execution) (2) Delayed instruction This instruction may be executed as a delayed instruction by writing it directly after a branch instruction with the “d” bit included. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 162: Sla %Rd, Imm5

    (after execution) (2) Delayed instruction This instruction may be executed as a delayed instruction by writing it directly after a branch instruction with the “d” bit included. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 163: Sll %Rd, %Rs

    (after execution) (2) Delayed instruction This instruction may be executed as a delayed instruction by writing it directly after a branch instruction with the “d” bit included. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 164: Sll %Rd, Imm5

    (after execution) (2) Delayed instruction This instruction may be executed as a delayed instruction by writing it directly after a branch instruction with the “d” bit included. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 165: Slp

    SLEEP mode. Refer to the technical manual of each model for details of SLEEP mode. Example ; The processor is placed in SLEEP mode. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 166: Sra %Rd, %Rs

    Sign bit (after execution) S ... S (2) Delayed instruction This instruction may be executed as a delayed instruction by writing it directly after a branch instruction with the “d” bit included. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 167: Sra %Rd, Imm5

    Sign bit (after execution) S ... S (2) Delayed instruction This instruction may be executed as a delayed instruction by writing it directly after a branch instruction with the “d” bit included. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 168: Srl %Rd, %Rs

    (after execution) (2) Delayed instruction This instruction may be executed as a delayed instruction by writing it directly after a branch instruction with the “d” bit included. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 169: Srl %Rd, Imm5

    (after execution) (2) Delayed instruction This instruction may be executed as a delayed instruction by writing it directly after a branch instruction with the “d” bit included. EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 170: Sub %Rd, %Rs

    “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Example (1) sub %r0,%r0 ; r0 = r0 - r0 (2) ext 0x1fff %r1,%r2 ; r1 = r2 - 0x3fff EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 171: Sub %Rd, Imm6

    “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Example (1) sub %r0,0x3f ; r0 = r0 - 0x3f (2) ext 0x1fff 0x1fff %r1,0x3f ; r1 = r1 - 0xffffffff EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 172: Sub %Sp, Imm10

    32 bits prior to the operation. (2) Delayed instruction This instruction may be executed as a delayed instruction by writing it directly after a branch instruction with the “d” bit. Example %sp,0x100 ; sp = sp - 0x400 EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 173: Swap %Rd, %Rs

    (2) Delayed instruction This instruction may be executed as a delayed instruction by writing it directly after a branch instruction with the “d” bit. Example When r1 = 0x87654321 ; r0 ← 0x21436587 swap %r0,%r1 EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 174: Swaph %Rd, %Rs

    (2) Delayed instruction This instruction may be executed as a delayed instruction by writing it directly after a branch instruction with the “d” bit. Example When r1 = 0x12345678 ; 0x34127856 → r2 swaph %r2,%r1 EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 175: Xor %Rd, %Rs

    “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Example (1) xor %r0,%r0 ; r0 = r0 ^ r0 (2) ext 0x1fff %r1,%r2 ; r1 = r2 ^ 0x00003fff EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 176: Xor %Rd, Sign6

    “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Example (1) xor %r0,0x3e ; r0 = r0 ^ 0xfffffffe (2) ext 0x7ff %r1,0x3f ; r1 = r1 ^ 0x0001ffff EPSON S1C33 FAMILY C33 PE CORE MANUAL...

  • Page 177: Appendix Instruction Code List (In Order Of Codes)

    × sign8 jreq sign8 × sign8 jreq.d sign8 × sign8 jrne sign8 × sign8 jrne.d sign8 × sign8 call sign8 × sign8 call.d sign8 × sign8 sign8 × sign8 jp.d sign8 EPSON S1C33 FAMILY C33 PE CORE MANUAL...
  • Page 178 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mnemonic Cycle Extension Delayed S Class imm6,sign6 imm6 %rd,imm6 imm6 %rd,imm6 sign6 %rd,sign6 sign6 ld.w %rd,sign6 sign6 %rd,sign6 sign6 %rd,sign6 sign6 %rd,sign6 sign6 %rd,sign6 EPSON S1C33 FAMILY C33 PE CORE MANUAL...
  • Page 179 ∗1 The ld.w %rd,%pc instruction must be executed as a delayed slot instruction. If it does not follow a delayed branch instruction, the PC value that is loaded into the rd register may not be the next instruction address to the ld.w instruction. EPSON S1C33 FAMILY C33 PE CORE MANUAL...
  • Page 180 Riesstrasse 15 Hi- Tech Park, Shenzhen 80992 Munich, GERMANY Phone: +86-755-2699-3828 Fax: +86-755-2699-3838 Phone: +49-89-14005-0 Fax: +49-89-14005-110 EPSON TAIWAN TECHNOLOGY & TRADING LTD. DÜSSELDORF BRANCH OFFICE 14F, No. 7, Song Ren Road Altstadtstrasse 176 Taipei 110 51379 Leverkusen, GERMANY Phone: +886-2-8786-6688...
  • Page 181 S1C33 Family C33 PE Core Manual SEMICONDUCTOR OPERATIONS DIVISION EPSON Electronic Devices Website http://www.epsondevice.com Document code: 410755500 Issue July, 2006 Printed in Japan...

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