0X5041: Watchdog Timer Status Register (Wdt_St) - Epson S1C17704 Technical Manual

17 WATCHDOG TIMER (WDT)

0x5041: Watchdog Timer Status Register (WDT_ST)

Register name Address Bit
Watchdog 0x5041 D7–2 –
Timer Status (8 bits)
Register D1
(WDT_ST)
D0
D[7:2] Reserved
D1 WDTMD: NMI/Reset Mode Select Bit
Selects either NMI or reset to be generated when the counter overflows.
1 (R/W): Reset
0 (R/W): NMI (default)
When this bit is set to 1, a reset signal will be output when the counter overflows. When this bit is set to
0, an NMI signal will be output.
D0 WDTST: NMI Status Bit
Indicates that an NMI has occurred due to a counter overflow.
1 (R): NMI has occurred (counter overflowed)
0 (R): NMI has not occurred (default)
This bit is provided to check if an NMI has occurred by the watchdog timer. WDTST being set to 1 can
be cleared to 0 by resetting the watchdog timer.
This bit is also set due to a counter overflow even if reset output is selected, however, the bit is cleared
at initial reset and cannot be checked if it has been set to 1.
17-6
Name Function
reserved
WDTMD NMI/Reset mode select
WDTST NMI status
Setting
–
1 Reset 0 NMI
1 NMI occurred 0 Not occurred
EPSON
Init. R/W Remarks
– – 0 when being read.
0 R/W
0 R
S1C17704 TECHNICAL MANUAL