Epson S1C17704 Technical Manual page 63

Level trigger mode
In level trigger mode, the ITC continuously samples interrupt signals at every rising edge of the system clock.
The interrupt flag (EIFTx) is set to 1 when a high level is sampled and is reset to 0 when a low level is sampled.
In this mode, writing 1 cannot reset the interrupt flag (EIFTx). Therefore, the interrupt source module must hold
the interrupt signal to high until the S1C17 Core accepts the interrupt request and must reset the interrupt signal
after that.
Interrupt signal
from an interrupt source
Interrupt flag in ITC
Note: The following S1C17704 interrupts use level trigger mode. The interrupt handler routine must
reset (write 1 to) the interrupt flag provided in the peripheral module, not EIFTx.
• P0 port interrupt
• P1 port interrupt
• Stopwatch timer interrupt
• Clock timer interrupt
• 8-bit OSC1 timer interrupt
• SVD interrupt
• LCD interrupt
• PWM & capture timer interrupt
For the interrupt flag to be reset, see the description for each peripheral module.
S1C17704 TECHNICAL MANUAL
pclk
Figure 6.3.5.2 Level Trigger Mode
6 INTERRUPT CONTROLLER (ITC)
The interrupt source negates the interrupt signal.
EPSON
6-7