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13.7 PWM & Capture Timer Interrupt
The T16E module can generate the following two types of interrupts:
• Compare A match interrupt
• Compare B match interrupt
The T16E module has one interrupt signal to be output to the interrupt controller (ITC) and it is shared with the two
causes of interrupt. To determine the cause of interrupt that has occurred, read the interrupt flags in the T16E mod-
ule.
Compare A match interrupt
This interrupt request occurs when the count of the counter matches the set value of the compare data A register
during count-up, and it sets the interrupt flag CAIF (D0/T16E_IFLG register) in the T16E module to 1.
∗ CAIF: Compare A Interrupt Flag in the PWM Timer Interrupt Flag (T16E_IFLG) Register (D0/0x530c)
Set the CAIE bit (D0/T16E_IMSK register) to 1 when using this interrupt. If CAIE is set to 0 (default), CAIF
will not be set to 1 and an interrupt request by this cause will not be sent to the ITC.
∗ CAIE: Compare A Interrupt Enable Bit in the PWM Timer Interrupt Mask (T16E_IMSK) Register (D0/0x530a)
If CAIF is set to 1, the T16E module outputs the interrupt request signal to the ITC. The interrupt request signal
sets the PWM & capture timer interrupt flag in the ITC to 1 and an interrupt occurs if other interrupt conditions
meet the ITC and S1C17 Core settings.
The PWM & capture timer interrupt handler routine should read the CAIF flag to check if the interrupt has oc-
curred due to a compare A match or another cause.
Furthermore, the interrupt handler routine must reset (write 1 to) CAIF in the T16E module, not the PWM &
capture timer interrupt flag in the ITC, to clear the cause of interrupt.
Compare B match interrupt
This interrupt request occurs when the count of the counter matches the set value of the compare data B register
during count-up, and it sets the interrupt flag CBIF (D1/T16E_IFLG register) in the T16E module to 1.
∗ CBIF: Compare B Interrupt Flag in the PWM Timer Interrupt Flag (T16E_IFLG) Register (D1/0x530c)
Set the CBIE bit (D1/T16E_IMSK register) to 1 when using this interrupt. If CBIE is set to 0 (default), CBIF
will not be set to 1 and an interrupt request by this cause will not be sent to the ITC.
∗ CBIE: Compare B Interrupt Enable Bit in the PWM Timer Interrupt Mask (T16E_IMSK) Register (D1/0x530a)
If CBIF is set to 1, the T16E module outputs the interrupt request signal to the ITC. The interrupt request signal
sets the PWM & capture timer interrupt flag in the ITC to 1 and an interrupt occurs if other interrupt conditions
meet the ITC and S1C17 Core settings.
The PWM & capture timer interrupt handler routine should read the CBIF flag to check if the interrupt has oc-
curred due to a compare B match or another cause.
Furthermore, the interrupt handler routine must reset (write 1 to) CBIF in the T16E module, not the PWM &
capture timer interrupt flag in the ITC, to clear the cause of interrupt.
Note: To avoid occurrence of unnecessary interrupts, be sure to reset the CAIF or CBIF flag before the
compare A match or compare B match interrupt is enabled using CAIE or CBIE.
S1C17704 TECHNICAL MANUAL
13 PWM & CAPTURE TIMER (T16E)
EPSON
13-9
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