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Sampling clock
SIN
Receive data buffer
RDRY
RD2B
RXD[7:0]
Interrupt
Disabling data transmission/reception
After data transfer (both transmission and reception) has finished, write 0 to the RXEN bit to disable data
transmission/reception.
Always make sure that the TDBE flag is 1 and TRBS and RDRY flags are 0 before data transmission/reception
is disabled.
When the RXEN bit is set to 0, the transmit and receive data buffers are placed in empty status (data is cleared
if any remains). Furthermore, the data being transferred cannot be guaranteed if RXEN is set to 0 during
transmitting/receiving.
S1C17704 TECHNICAL MANUAL
data 1
data 2
S1 D0 ··· P S2 S1 D0 ··· P S2 S1 D0 ··· P S2 S1 D0 ··· P S2 S1 D0 ··· P S2 S1 D0 ··· P S2
data 1
–
Rd
data 1
Receive buffer full interrupt request
S1: Start bit, S2: Stop bit, P: Parity bit, Rd: Data read from RXD[7:0]
Figure 18.5.2 Data Receive Timing Chart
EPSON
data 3
data 4
data 2
data 2, 3 data 3
Rd
data 2
(RBFI = 0)
18 UART
data 5
data 6
data 3, 4
data 3
Overrun error
interrupt request
18-7
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