Lcd Interrupt - Epson S1C17704 Technical Manual

22.7 LCD Interrupt

The LCD module can generate an interrupt by the frame signal.
Frame interrupt
This interrupt request occurs in every frame, and it sets the interrupt flag FRMIF (D0/LCD_IFLG register) in
the LCD module to 1.
See Figures 22.4.1 and 22.4.2 for the interrupt timings.
∗ FRMIF: Frame Signal Interrupt Flag in the LCD Interrupt Flag (LCD_IFLG) Register (D0/0x50a6)
Set the FRMIE (D0/LCD_IMSK register) to 1 when using this interrupt. If FRMIE is set to 0 (default), an
interrupt request by this cause will not be sent to the interrupt controller (ITC).
∗ FRMIE: Frame Signal Interrupt Enable Bit in the LCD Interrupt Mask (LCD_IMSK) Register (D0/0x50a5)
If FRMIF is set to 1 when the FRMIE has been set to 1 (interrupt enabled), the LCD module outputs the
interrupt request signal to the ITC. The interrupt request signal sets the LCD interrupt flag in the ITC to 1 and
an interrupt occurs if other interrupt conditions meet the ITC and S1C17 Core settings.
The interrupt handler routine must reset (write 1 to) FRMIF in the LCD module, not the LCD interrupt flag in
the ITC, to clear the cause of interrupt.
Note: To avoid occurrence of unnecessary interrupts, be sure to reset the FRMIF flag before the LCD
interrupt is enabled using FRMIE.
ITC registers for LCD interrupt
According to the interrupt condition settings shown above, the LCD asserts the interrupt signal sent to the
ITC at the rising edge of the frame signal. To generate an LCD interrupt, set the interrupt level and enable the
interrupt using the ITC registers. The following shows the control bits for the LCD interrupt in the ITC.
Interrupt flag in the ITC
∗ EIFT6: LCD Interrupt Flag in the Interrupt Flag (ITC_IFLG) Register (D6/0x4300)
Interrupt enable bit in the ITC
∗ EIEN6: LCD Interrupt Enable Bit in the Interrupt Enable (ITC_EN) Register (D6/0x4302)
Interrupt level setup bits in the ITC
∗ EILV6[2:0]: LCD Interrupt Level Bits in the External Interrupt Level Setup (ITC_ELV3) Register 3 (D[2:0]/0x430c)
Interrupt trigger mode select bit in the ITC (fixed at 1)
∗ EITG6: LCD Interrupt Trigger Mode Select Bit in the External Interrupt Level Setup (ITC_ELV3) Register 3
(D4/0x430c)
The LCD interrupt signal sets EIFT6 to 1.
If EIEN6 has been set to 1, the ITC sends an interrupt request to the S1C17 Core. To disable the LCD interrupt,
set EIEN6 to 0. EIFT6 is always set to 1 by the interrupt signal sent from the LCD module, regardless of how
EIEN6 is set (even when set to 0).
EILV6[2:0] sets the interrupt level (0 to 7) of the LCD interrupt.
An interrupt request to the S1C17 Core is accepted only when all the conditions described below are met.
• The interrupt enable bit is set to 1.
• The IE (Interrupt Enable) bit of the PSR (Processor Status Register) in the S1C17 Core is set to 1.
• The LCD interrupt has a higher interrupt level than the value that is set in the IL field of the PSR.
• No other cause of interrupt having higher priority, such as NMI, has occurred.
For details on these interrupt control registers, as well as the device operation when an interrupt has occurred,
see Chapter 6, "Interrupt Controller (ITC)."
S1C17704 TECHNICAL MANUAL
EPSON
22 LCD DRIVER (LCD)
22-11