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3 MEMORY MAP, BUS CONTROL
3.4 Display RAM Area
3.4.1 Display RAM
The display RAM for the on-chip LCD driver is located in the 576-byte area from address 0x80000 to address
0x8055f. The display RAM is accessed in two to five cycles as an eight-bit device. It can be used as a general-
purpose RAM when it is not used for display. See Section 22.5, "Display Memory," for details of the display
memory.
3.4.2 Access Control for the SRAM Controller
The S1C17704 display RAM is accessed via the exclusive SRAM controller. A MISC register is used to set the
access condition for the SRAM controller.
Setting number of access cycles for the SRAM controller
In order to read/write data from/to the display RAM properly, set the appropriate number of access cycles
according to the CCLK frequency using the SRCYC[1:0] bits (D[1:0]/ MISC_SR register).
0x5321: SRAMC Control Register (MISC_SR)
Register name Address
Bit
SRAMC Control
0x5321
D7–2 –
Register
(8 bits)
D1–0 SRCYC[1:0] SRAMC access cycle
(MISC_SR)
D[7:2]
Reserved
D[1:0]
SRCYC[1:0]: SRAMC Access Cycle Setup Bits
Sets the number of SRAM (display RAM) controller access cycle.
SRCYC[1:0]
3-6
Name
Function
reserved
Table 3.4.2.1 Setting Access Cycles for the SRAM Controller
Number of access cycles
0x3
0x2
0x1
0x0
Setting
–
SRCYC[1:0]
Access cycle
0x3
0x2
0x1
0x0
5 cycles
4 cycles
3 cycles
2 cycles
EPSON
Init. R/W
Remarks
–
–
0 when being read.
0x3 R/W
5 cycles
4 cycles
3 cycles
2 cycles
CCLK frequency
8.2 MHz max.
8.2 MHz max.
8.2 MHz max.
6 MHz max.
(Default: 0x3)
S1C17704 TECHNICAL MANUAL
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