Page 1 MF1074 - 03 CMOS 4 - BIT SINGLE CHIP MICROCOMPUTER S1C63454 Technical Manual S1C63454 Technical Hardware...
Page 2 No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any...
Page 3 Revisions and Additions for this manual Chapter Section Page Item Contents OSC1 crystal oscillation circuit The table was revised. Appendix Appendix The Appendix was added.
Page 5 The information of the product number change Starting April 1, 2001, the product number has been changed as listed below. Please use the new product number when you place an order. For further information, please contact Epson sales representative. Configuration of product number...
Page 7: Table Of Contents
4.4 Input Ports (K00–K03) ................27 4.4.1 Configuration of input ports ..............27 4.4.2 Interrupt function ..................27 4.4.3 Mask option ....................28 4.4.4 I/O memory of input ports ................. 29 4.4.5 Programming notes ................... 30 EPSON S1C63454 TECHNICAL MANUAL...
Page 8 4.11.2 Mask option ..................... 70 4.11.3 Master mode and slave mode of serial interface ........70 4.11.4 Data input/output and interrupt function ..........71 4.11.5 I/O memory of serial interface ..............74 4.11.6 Programming notes ................. 77 EPSON S1C63454 TECHNICAL MANUAL...
Page 9 OARD FOR A.1 Names and Functions of Each Part ............111 A.2 Connecting to the Target System ..............114 A.3 Usage Precautions ..................116 A.3.1 Operational precautions ................116 A.3.2 Differences with the actual IC ..............116 EPSON S1C63454 TECHNICAL MANUAL...
Page 11: Chapter Utline
CHAPTER UTLINE The S1C63454 is a microcomputer which has a high-performance 4-bit CPU S1C63000 as the core CPU, ROM (4,096 words × 13 bits), RAM (1,024 words × 4 bits), serial interface, watchdog timer, program- mable timer, time base counters (2 systems), a dot-matrix LCD driver that can drive a maximum 40 segments ×...
Page 12: Block Diagram
2,048 words × 4 bits Programmable Timer COM0–16 LCD Driver 40 SEG × 17 COM SEG0–39 K00–K03 Input Port TEST Serial Interface – Power CA–CF Controller P00–P03 I/O Port P10–P13 Sound Output Port R00–R03 Generator Fig. 1.2.1 Block diagram EPSON S1C63454 TECHNICAL MANUAL...
Page 13: Pin Layout Diagram
COM1 COM13 SEG18 COM0 COM14 SEG17 COM15 SEG16 COM16 SEG15 OSC1 SEG39 SEG14 OSC2 SEG38 SEG13 N.C. SEG37 SEG12 OSC3 N.C. SEG36 SEG11 OSC4 N.C. SEG35 SEG10 N.C. : No Connection Fig. 1.3.1 Pin layout diagram EPSON S1C63454 TECHNICAL MANUAL...
Page 14: Pin Description
The function option generator winfog, that has been prepared as the development software tool of S1C63454, is used for this selection. Mask pattern of the IC is finally generated based on the data created by the winfog. Refer to the "S5U1C63000A Manual"...
Page 15 Refer to Section 4.3.2, "OSC1 oscillation circuit", for details. (10)OSC3 oscillation circuit Either CR oscillation circuit or ceramic oscillation circuit can be selected as the OSC3 oscillation circuit. Refer to Section 4.3.3, "OSC3 oscillation circuit", for details. EPSON S1C63454 TECHNICAL MANUAL...
Page 16 CHAPTER 1: OUTLINE <Mask option list> The following is the option list for the S1C63454. Multiple selections are available in each option item as indicated in the option list. Refer to Chapter 4, "Peripheral Circuits and Operation", to select the specifica- tions that meet the application system.
Page 17: Ower Upply And
The S1C63454 operates by applying a single power supply within the above range between V and V The S1C63454 itself generates the voltage necessary for all the internal circuits by the built-in power supply circuits shown in Table 2.1.2. Table 2.1.2 Power supply circuits...
Page 18: Voltage
The S1C63454 is designed with twin clock specification; it has two types of oscillation circuits OSC1 and OSC3 built-in. Use OSC1 clock for normal operation, and switch it to OSC3 by the software when high- speed operation is necessary.

Page 19: Initial Reset
CHAPTER 2: POWER SUPPLY AND INITIAL RESET 2.2 Initial Reset To initialize the S1C63454 circuits, initial reset must be executed. There are two ways of doing this. (1) External initial reset by the RESET terminal (2) External initial reset by simultaneous low input to terminals K00–K03 (mask option setting) The circuits are initialized by either (1) or (2).
Page 20: Simultaneous Low Input To Terminals K00-K03
If an instruction which does not permit extended operation is used as the following instruction, the operation is not guaranteed. Therefore, do not write data to the EXT register for initialization only. Refer to the "S1C63000 Core CPU Manual" for extended addressing and usable instructions. EPSON S1C63454 TECHNICAL MANUAL...
Page 21: Terminal Settings At Initial Resetting
For setting procedure of the functions, see explanations for each of the peripheral circuits. 2.3 Test Terminal (TEST) This is the terminal used for the factory inspection of the IC. During normal operation, connect the TEST terminal to V EPSON S1C63454 TECHNICAL MANUAL...
Page 22: Chapter 3 Cpu, Rom, Ram
The core CPU can linearly access the program space up to step FFFFH from step 0000H, however, the program area of the S1C63454 is step 0000H to step 0FFFH. The program start address after initial reset is assigned to step 0110H. The non-maskable interrupt (NMI) vector and hardware interrupt vectors are allocated to step 0100H and steps 0104H–010EH, respectively.
Page 23: Data Rom
2,048 words × 4 bits. The data ROM is assigned to addresses 8000H to 87FFH on the data memory map, and the data can be read using the same data memory access instructions as the RAM. EPSON S1C63454 TECHNICAL MANUAL...
Page 24: Peripheral Circuits And Operation
IRCUITS AND PERATION The peripheral circuits of S1C63454 (timer, I/O, etc.) are interfaced with the CPU in the memory mapped I/O method. Thus, all the peripheral circuits can be controlled by accessing the I/O memory on the memory map using the memory operation instructions. The following sections explain the detailed operation of each peripheral circuit.
Page 25 IOC10 Output Input P10 I/O control register (ESIF=0) functions as a general-purpose register when SIF is selected Remarks ∗1 Initial value at initial reset ∗2 Not set in the circuit ∗3 Constantly "0" when being read EPSON S1C63454 TECHNICAL MANUAL...
Page 26 MSB first LSB first Serial I/F data input/output permutation SCPS Serial I/F clock phase selection SCPS SCS1 SCS0 –Negative polarity (mask option) FF71H [SCS1, 0] –Positive polarity (mask option) Clock Slave SCS1 Serial I/F [SCS1, 0] SCS0 clock mode selection Clock OSC1/2 OSC1 EPSON S1C63454 TECHNICAL MANUAL...
Page 27 RLD01 RLD00 RLD07 RLD07 RLD06 RLD05 RLD04 RLD06 Programmable timer 0 reload data (high-order 4 bits) FFC5H RLD05 RLD04 RLD13 RLD13 RLD12 RLD11 RLD10 RLD12 Programmable timer 1 reload data (low-order 4 bits) FFC6H RLD11 RLD10 EPSON S1C63454 TECHNICAL MANUAL...
Page 28 Interrupt factor flag (Clock timer 32 Hz) ∗3 ∗2 – Unused ISW1 ISW10 ∗3 ∗2 – Unused FFF7H ISW1 Interrupt factor flag (Stopwatch timer 1 Hz) ISW10 Reset Invalid Interrupt factor flag (Stopwatch timer 10 Hz) EPSON S1C63454 TECHNICAL MANUAL...
Page 29: Watchdog Timer
4.2.1 Configuration of watchdog timer The S1C63454 has a built-in watchdog timer that operates with a 256 Hz divided clock from the OSC1 as the source clock. The watchdog timer starts operating after initial reset, however, it can be stopped by the software.
Page 30: I/O Memory Of Watchdog Timer
(1) When the watchdog timer is being used, the software must reset it within 3-second cycles. (2) Because the watchdog timer is set in operation state by initial reset, set the watchdog timer to disabled state (not used) before generating an interrupt (NMI) if it is not used. EPSON S1C63454 TECHNICAL MANUAL...
Page 31: Oscillation Circuit
4.3.1 Configuration of oscillation circuit The S1C63454 has two oscillation circuits (OSC1 and OSC3). OSC1 is either a crystal or a CR oscillation circuit that supplies the operating clock to the CPU and peripheral circuits. OSC3 is either a CR or a ceramic oscillation circuit.
Page 32: Osc1 Oscillation Circuit
Pay special attention to the circuits that use f as the source clock, such as the timer (time OSC1 lag), the LCD frame frequency (display quality, flicker in low frequency) and the sound generator (sound quality). EPSON S1C63454 TECHNICAL MANUAL...
Page 33: Osc3 Oscillation Circuit
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) 4.3.3 OSC3 oscillation circuit The S1C63454 has built-in the OSC3 oscillation circuit that generates the CPU's sub-clock (Max. 4 MHz) for high speed operation and the source clock for peripheral circuits needing a high speed clock (pro- grammable timer, FOUT output).
Page 34: Switching Of Operating Voltage
OSC3 operation: = 2.2 V Since the S1C63454 fixes the V voltage value at 2.2 V when the CR oscillation circuit is selected as the OSC1 oscillation circuit by mask option, it is not necessary to switch the operating voltage V software (VDC register).
Page 35: I/O Memory Of Oscillation Circuit
OSC3 is not performed. When the CR oscillation circuit has been selected as the OSC1 oscillation circuit by mask option, setting VDC to "0" makes no difference. At initial reset, this register is set to "0". EPSON S1C63454 TECHNICAL MANUAL...
Page 36: Programming Notes
V using the VDC register and the V voltage is fixed at 2.2 V. The V level does not change even if any data is written to the VDC register. EPSON S1C63454 TECHNICAL MANUAL...
Page 37: Input Ports (K00-K03)
4.4 Input Ports (K00–K03) 4.4.1 Configuration of input ports The S1C63454 has four bits general-purpose input ports. Each of the input port terminals (K00–K03) provides internal pull-up resistor. Pull-up resistor can be selected for each bit with the mask option.
Page 38: Mask Option
Internal pull-up resistor can be selected for each of the four bits of the input ports (K00–K03) with the input port mask option. When "Gate direct" is selected, take care that the floating status does not occur for the input. Select "With pull-up resistor" for input ports that are not being used. EPSON S1C63454 TECHNICAL MANUAL...
Page 39: I/O Memory Of Input Ports
When "0" is written: Rising edge Reading: Valid The interrupt conditions can be set for the rising or falling edge of input for each of the four bits (K00– K03), through the input comparison registers (KCP00–KCP03). EPSON S1C63454 TECHNICAL MANUAL...
Page 40: Programming Notes
"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state. EPSON S1C63454 TECHNICAL MANUAL...
Page 41: Output Ports (R00-R03)
(R00–R03) 4.5.1 Configuration of output ports The S1C63454 has 4 bits of general output ports. Output specifications of the output ports can be selected individually with the mask option. Two kinds of output specifications are available: complementary output and N-channel open drain output.
Page 42: High Impedance Control
R02 and R03 registers when the special output has been selected. • Be aware that the output terminal shifts into high impedance status when "1" is written to the high impedance control register (R02HIZ, R03HIZ). EPSON S1C63454 TECHNICAL MANUAL...
Page 43 Note: A hazard may occur when the FOUT signal is turned ON and OFF. Figure 4.5.4.3 shows the output waveform of the FOUT signal. R03HIZ register Fix at "0" R03 register Fix at "1" FOUTE register "0" "1" "0" FOUT output Fig. 4.5.4.3 Output waveform of FOUT signal EPSON S1C63454 TECHNICAL MANUAL...
Page 44: I/O Memory Of Output Ports
(V When the output ports R02 and R03 are used for special output (TOUT, FOUT), fix the R02 register and the R03 register at "1". At initial reset, these registers are all set to "1". EPSON S1C63454 TECHNICAL MANUAL...
Page 45: Programming Notes
(2) A hazard may occur when the FOUT signal and the TOUT signal are turned ON and OFF. (3) When f is selected for the FOUT signal frequency, it is necessary to control the OSC3 oscillation OSC3 circuit before output. Refer to Section 4.3, "Oscillation Circuit", for the control and notes. EPSON S1C63454 TECHNICAL MANUAL...
Page 46: I/O Ports (P00-P03 And P10-P13)
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) 4.6 I/O Ports (P00–P03 and P10–P13) 4.6.1 Configuration of I/O ports The S1C63454 has eight bits of general-purpose I/O ports. Figure 4.6.1.1 shows the configuration of the I/ O port. Pull-up control...
Page 47: Mask Option
I/O control. (See Table 4.6.1.1.) 4.6.4 Pull-up during input mode A pull-up resistor that operates during the input mode is built into each I/O port of the S1C63454. Mask option can set the use or non-use of this pull-up.
Page 48: I/O Memory Of I/O Ports
Serial I/F clock trigger (writing) FF70H Stop Serial I/F clock status (reading) ESIF Serial I/F enable (P1 port function selection) *1 Initial value at initial reset *2 Not set in the circuit *3 Constantly "0" when being read EPSON S1C63454 TECHNICAL MANUAL...
Page 49 Make this waiting time the amount of time or more calculated by the following expression. 10 × C × R C: terminal capacitance 5 pF + parasitic capacitance ? pF R: pull-up resistance 330 k Ω EPSON S1C63454 TECHNICAL MANUAL...
Page 50: Programming Note
Particular care needs to be taken of the key scan during key matrix configuration. Make this waiting time the amount of time or more calculated by the following expression. 10 × C × R C: terminal capacitance 5 pF + parasitic capacitance ? pF R: pull-up resistance 330 kΩ EPSON S1C63454 TECHNICAL MANUAL...
Page 51: Lcd Driver (Com0-Com16, Seg0-Seg39)
4.7 LCD Driver (COM0–COM16, SEG0–SEG39) 4.7.1 Configuration of LCD driver The S1C63454 has 17 common terminals (COM0–COM16) and 40 segment terminals (SEG0–SEG39), so that it can drive a dot matrix type LCD with a maximum of 680 (40 × 17) dots.
Page 52: Mask Option
ALOFF, ALON (all ON) has priority over the ALOFF (all OFF). (2) Switching of drive duty In the S1C63454, the drive duty can be set to 1/17, 1/16 or 1/8 by the software. This setting is done using the LDUTY1 and LDUTY0 registers as shown in Table 4.7.4.1.
Page 53 ..1/17 Frame signal 32 Hz ∗ ∗ When f = 32.768 kHz OSC1 C2 ( COM0 C2 ( COM1 C2 ( COM2 C2 ( SEG0 C2 ( SEG1 Fig. 4.7.4.1 Drive waveform for 1/4 bias EPSON S1C63454 TECHNICAL MANUAL...
Page 54 1/16 ..1/17 Frame signal 32 Hz ∗ ∗ When f = 32.768 kHz OSC1 COM0 COM1 COM2 SEG0 SEG1 Fig. 4.7.4.2 Drive waveform for 1/5 bias EPSON S1C63454 TECHNICAL MANUAL...
Page 55: Display Memory
F107H ..F14FH COM6 COM7 Unused F200H F202H F204H F206H ..F24EH (b) When 1/8 duty is selected Fig. 4.7.5.1 Correspondence between display memory and LCD dot matrix EPSON S1C63454 TECHNICAL MANUAL...
Page 56: Lcd Contrast Adjustment
Note: When a program that access no memory mounted area (F050H–F0FFH, F150H–F1FFH, F201H, F203H, · · ·, F24FH) is made, the operation is not guaranteed. 4.7.6 LCD contrast adjustment In the S1C63454, the LCD contrast can be adjusted by the software. It is realized by controlling the voltages V and V output from the LCD system voltage circuit.
Page 57: I/O Memory Of Lcd Driver
It takes about 100 msec for the LCD drive voltage to stabilize after starting up the LCD system voltage circuit by writing "1" to the LPWR register. At initial reset, this register is set to "0". EPSON S1C63454 TECHNICAL MANUAL...
Page 58 By writing "1" to the ALOFF register, all the LCD dots goes OFF, and when "0" is written, it returns to normal display. This function outputs an OFF waveform to the SEG terminals, and does not affect the content of the display memory. At initial reset, this register is set to "1". EPSON S1C63454 TECHNICAL MANUAL...
Page 59: Programming Notes
(2) Because at initial reset, the contents of display memory and LC3–LC0 (LCD contrast) are undefined, there is need to initialize by the software. Furthermore, take care of the registers LPWR and ALOFF because these are set so that the display goes OFF. EPSON S1C63454 TECHNICAL MANUAL...
Page 60: Clock Timer
4.8 Clock Timer 4.8.1 Configuration of clock timer The S1C63454 has a built-in clock timer that uses OSC1 (crystal oscillator) as the source oscillator. The clock timer is configured of an 8-bit binary counter that serves as the input clock, f...
Page 61: Interrupt Function
(EIT0, EIT1, EIT2, EIT3). However, regardless of the interrupt mask register setting, the interrupt factor flag is set to "1" at the falling edge of the corresponding signal. EPSON S1C63454 TECHNICAL MANUAL...
Page 62: I/O Memory Of Clock Timer
The clock timer is reset by writing "1" to TMRST. When the clock timer is reset in the RUN status, opera- tion restarts immediately. Also, in the STOP status the reset data is maintained. No operation results when "0" is written to TMRST. This bit is write-only, and so is always "0" at reading. EPSON S1C63454 TECHNICAL MANUAL...
Page 63 RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state. At initial reset, these flags are set to "0". EPSON S1C63454 TECHNICAL MANUAL...
Page 64: Programming Notes
(3) When the CR oscillation circuit is selected as the OSC1 oscillation circuit by mask option, the frequen- cies and times differ from the values described in this section because the oscillation frequency will be 60 kHz (Typ.). Therefore, the clock timer can not be used for the clock function. EPSON S1C63454 TECHNICAL MANUAL...
Page 65: Stopwatch Timer
4.9 Stopwatch Timer 4.9.1 Configuration of stopwatch timer The S1C63454 has 1/100 sec unit and 1/10 sec unit stopwatch timer built-in. The stopwatch timer is configured with a 2 levels 4-bit BCD counter which has an input clock approximating 100 Hz signal (signal divided from OSC1 to the closest 100 Hz) and data can be read in units of 4 bits by software.
Page 66: Interrupt Function
The respective interrupts can be masked separately using the interrupt mask registers (EISW10 and EISW1). However, regardless of the setting of the interrupt mask registers, the interrupt factor flags are set to "1" by the overflow of their corresponding counters. EPSON S1C63454 TECHNICAL MANUAL...
Page 67: I/O Memory Of Stopwatch Timer
In the STOP status, the timer data is maintained until the next RUN status or the timer is reset. Also, when the STOP status changes to the RUN status, the data that is maintained can be used for resuming the count. EPSON S1C63454 TECHNICAL MANUAL...
Page 68: Programming Notes
(3) When the CR oscillation circuit is selected as the OSC1 oscillation circuit by mask option, the frequen- cies and times differ from the values described in this section because the oscillation frequency will be 60 kHz (Typ.). Therefore, this timer can not be used for the stopwatch function. EPSON S1C63454 TECHNICAL MANUAL...
Page 69: Programmable Timer
4.10.1 Configuration of programmable timer The S1C63454 has two 8-bit programmable timer systems (timer 0 and timer 1) built-in. Timer 0 and timer 1 are composed of 8-bit presettable down counters and they can be used as 8-bit × 2 channel programmable timers.
Page 70: Setting Of Initial Value And Counting Down
Interrupt generation Fig. 4.10.2.1 Basic operation timing of down counter Note: The counter mode selection register EVCNT should be set to "0" when timer 0 is used as a down counter. Otherwise it will cause malfunction. EPSON S1C63454 TECHNICAL MANUAL...
Page 71: Setting Of Input Clock In Timer Mode
(timer 1) to "1", and generates an interrupt. The interrupt can also be masked by setting the correspond- ing interrupt mask register EIPT0 (timer 0) or EIPT1 (timer 1). However, the interrupt factor flag is set to "1" by an underflow of the corresponding timer regardless of the interrupt mask register setting. EPSON S1C63454 TECHNICAL MANUAL...
Page 72: Setting Of Tout Output
ON and OFF by setting the register. Figure 4.10.5.3 shows the output waveform of the TOUT signal. R02HIZ register Fix at "0" R02 register Fix at "1" PTOUT register "0" "1" "0" TOUT output Fig. 4.10.5.3 Output waveform of the TOUT signal EPSON S1C63454 TECHNICAL MANUAL...
Page 73: Transfer Rate Setting For Serial Interface
Oscillation frequency (OSC1/OSC3) bps: Transfer rate (00H can be set to RLD1X) Be aware that the maximum clock frequency for the serial interface is limited to 1 MHz when OSC3 is used as the clock source. EPSON S1C63454 TECHNICAL MANUAL...
Page 74: I/O Memory Of Programmable Timer
Unused FFF2H IPT1 Interrupt factor flag (Programmable timer 1) IPT0 Reset Invalid Interrupt factor flag (Programmable timer 0) *1 Initial value at initial reset *2 Not set in the circuit *3 Constantly "0" when being read EPSON S1C63454 TECHNICAL MANUAL...
Page 75 EVCNT register, no function is selected and when "0" is written, the timer mode is selected. At initial reset, this register is set to "0". Note: The counter mode selection register EVCNT should be set to "0" when timer 0 is used as a down counter. Otherwise it will cause malfunction. EPSON S1C63454 TECHNICAL MANUAL...
Page 76 When STOP status changes to RUN status, the data that has been maintained can be used for resuming the count. Same as above, the timer 1 counter is controlled by the PTRUN1 register. At initial reset, these registers are set to "0". EPSON S1C63454 TECHNICAL MANUAL...
Page 77 RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state. At initial reset, these flags are set to "0". EPSON S1C63454 TECHNICAL MANUAL...
Page 78: Programming Notes
(write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state. (6) The counter mode selection register EVCNT should be set to "0" when timer 0 is used as a down counter. Otherwise it will cause malfunction. EPSON S1C63454 TECHNICAL MANUAL...
Page 79: Serial Interface (Sin, Sout, Sclk, Srdy)
The synchronous clock for serial data input/output may be set by selecting by software any one of three types of master mode (internal clock mode: when the S1C63454 is to be the master for serial input/ output) and a type of slave mode (external clock mode: when the S1C63454 is to be the slave for serial input/output).
Page 80: Mask Option
4.11.3 Master mode and slave mode of serial interface The serial interface of the S1C63454 has two types of operation mode: master mode and slave mode. The master mode uses an internal clock as the synchronous clock for the built-in shift register, and outputs this internal clock from the SCLK (P12) terminal to control the external (slave side) serial device.
Page 81: Data Input/Output And Interrupt Function
(1) Serial data output procedure and interrupt The S1C63454 serial interface is capable of outputting parallel data as serial data, in units of 8 bits. By setting the parallel data to the data registers SD0–SD3 (FF72H) and SD4–SD7 (FF73H) and writing "1"...
Page 82 (2) Serial data input procedure and interrupt The S1C63454 serial interface is capable of inputting serial data as parallel data, in units of 8 bits. The serial data is input from the SIN (P10) terminal, synchronizes with the synchronous clock, and is sequentially read in the 8-bit shift register.
Page 83 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) (5) Timing chart The S1C63454 serial interface timing charts are shown in Figures 4.11.4.2 and 4.11.4.3. SCTRG (W) SCTRG (R) SCLK 8-bit shift register SOUT ISIF SRDY (Slave mode) (a) When SCPS = "1"...
Page 84: I/O Memory Of Serial Interface
At initial reset, this register is set to "0". Note: After setting ESIF to "1", wait at least 10 µsec before starting actual data transfer since a hazard may be generated from the P12 (SCLK) terminal when ESIF is set to "1". EPSON S1C63454 TECHNICAL MANUAL...
Page 85 The input data fetch timing may be selected but output timing for output data is fixed at the falling edge of SCLK (when negative polarity is selected) or at the rising edge of SCLK (when positive polarity is selected). At initial reset, this register is set to "0". EPSON S1C63454 TECHNICAL MANUAL...
Page 86 ) level bit into "0", and is loaded to these registers. Perform data reading only while the serial interface is not running (i.e., the synchronous clock is neither being input or output). At initial reset, these registers are undefined. EPSON S1C63454 TECHNICAL MANUAL...
Page 87: Programming Notes
"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state. EPSON S1C63454 TECHNICAL MANUAL...
Page 88: Sound Generator
4.12 Sound Generator 4.12.1 Configuration of sound generator The S1C63454 has a built-in sound generator for generating buzzer signals. Hence, generated buzzer signals (BZ) can be output from the BZ terminal. Aside permitting the respective setting of the buzzer signal frequency and sound level to 8 stages, it permits the adding of a digital envelope by means of duty ratio control.
Page 89: Control Of Buzzer Output
Conversely, when BDTY0–BDTY2 have all been set to "1", the duty ratio becomes minimum and the sound level also becomes minimum. The duty ratio that can be set is different depending on the frequency that has been set, so see Table 4.12.4.2. EPSON S1C63454 TECHNICAL MANUAL...
Page 90: Digital Envelope
BZFQ0–2 ENON ENRST ENRTM BZ signal Level 1 (Max.) duty ratio 8 (Min.) = 62.5 msec = 125 msec –4 –4 = 62.5 msec = 125 msec 02–07 12–17 Fig. 4.12.5.1 Timing chart for digital envelope EPSON S1C63454 TECHNICAL MANUAL...
Page 91: One-Shot Output
One-shot output is invalid during normal buzzer output (during BZE = "1"). Figure 4.12.6.1 shows timing chart for one-shot output. 256 Hz SHTPW BZSHT (W) BZSHT (R) BZSTP BZ output (Negative polarity) BZ output (Positive polarity) Fig. 4.12.6.1 Timing chart for one-shot output EPSON S1C63454 TECHNICAL MANUAL...
Page 92: I/O Memory Of Sound Generator
Buzzer frequency (Hz) 4096.0 3276.8 2730.7 2340.6 2048.0 1638.4 1365.3 1170.3 Select the buzzer frequency from among the above 8 types that have divided the oscillation clock. At initial reset, this register is set to "0". EPSON S1C63454 TECHNICAL MANUAL...
Page 93 When "1" has been written in ENRTM, it becomes 125 msec (8 Hz) units and when "0" has been written, it becomes 62.5 msec (16 Hz) units. At initial reset, this register is set to "0". EPSON S1C63454 TECHNICAL MANUAL...
Page 94: Programming Notes
(3) The buzzer signal is generated by dividing the OSC1 oscillation clock. Since the frequencies and times that are described in this section are the values in the case of crystal oscillation (32.768 kHz, Typ.), they differ when CR oscillation (60 kHz, Typ.) is selected. EPSON S1C63454 TECHNICAL MANUAL...
Page 95: Interrupt And Halt
NMI are masked and interrupts cannot be accepted until the other one is set. <HALT> The S1C63454 has HALT functions that considerably reduce the current consumption when it is not necessary. The CPU enters HALT status when the HALT instruction is executed.
Page 96 SIK01 EIK0 KCP02 Interrupt flag SIK02 KCP03 SIK03 EIT3 EIT2 Interrupt factor flag Interrupt mask register EIT1 Input comparison register EIT0 Interrupt selection register ISW1 EISW1 ISW10 EISW10 Fig. 4.13.1 Configuration of the interrupt circuit EPSON S1C63454 TECHNICAL MANUAL...
Page 97: Interrupt Factor
"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state. EPSON S1C63454 TECHNICAL MANUAL...
Page 98: Interrupt Mask
Interrupt factor Priority 0100H Watchdog timer High 0104H Programmable timer 0106H Serial interface 0108H K00–K03 input 010CH Clock timer 010EH Stopwatch timer The four low-order bits of the program counter are indirectly addressed through the interrupt request. EPSON S1C63454 TECHNICAL MANUAL...
Page 99: I/O Memory Of Interrupt
ISW1 Interrupt factor flag (Stopwatch timer 1 Hz) ISW10 Reset Invalid Interrupt factor flag (Stopwatch timer 10 Hz) *1 Initial value at initial reset *2 Not set in the circuit *3 Constantly "0" when being read EPSON S1C63454 TECHNICAL MANUAL...
Page 100: Programming Notes
Further, when re-setting the stack pointer, the SP1 and SP2 must be set as a pair. When one of them is set, all the interrupts including NMI are masked and interrupts cannot be accepted until the other one is set. EPSON S1C63454 TECHNICAL MANUAL...
Page 101: Summary Of Notes
UMMARY OF OTES 5.1 Notes for Low Current Consumption The S1C63454 contains control registers for each of the circuits so that current consumption can be reduced. These control registers reduce the current consumption through programs that operate the circuits at the minimum levels.
Page 102: Summary Of Notes By Function
0000H to 00FFH. Therefore, pay attention to the SP1 value because it may be set to 0200H or more exceeding the 4-bit/16-bit accessible range in the S1C63454 or it may be set to 00FFH or less. Memory accesses except for stack operations by SP1 are 4-bit data access.
Page 103 (2) When the CR oscillation circuit is selected as the OSC1 oscillation circuit by mask option, the frequen- cies and times differ from the values described in this section because the oscillation frequency will be 60 kHz (Typ.). Therefore, this timer can not be used for the stopwatch function. EPSON S1C63454 TECHNICAL MANUAL...
Page 104 (3) The buzzer signal is generated by dividing the OSC1 oscillation clock. Since the frequencies and times that are described in this section are the values in the case of crystal oscillation (32.768 kHz, Typ.), they differ when CR oscillation (60 kHz, Typ.) is selected. EPSON S1C63454 TECHNICAL MANUAL...
Page 105 Further, when re-setting the stack pointer, the SP1 and SP2 must be set as a pair. When one of them is set, all the interrupts including NMI are masked and interrupts cannot be accepted until the other one is set. EPSON S1C63454 TECHNICAL MANUAL...
Page 106: Notes On Mounting
In particular, the V –V voltage affects the display quality. Do not connect anything to the V –V terminals when the LCD driver is not used. EPSON S1C63454 TECHNICAL MANUAL...
Page 107 (1) Design the product and implement the IC on the board so that it is shielded from visible radiation in actual use. (2) The inspection process of the product needs an environment that shields the IC from visible radiation. (3) As well as the face of the IC, shield the back and side too. EPSON S1C63454 TECHNICAL MANUAL...
Page 108: Basic External Wiring Diagram
Resistor for OSC3 CR oscillation 34 kΩ (1.8 MHz) 0.2 µF –C Capacitor 0.1 µF Capacitor 3.3 µF Capacitor 0.1 µF RESET terminal capacitor Note: The above table is simply an example, and is not guaranteed to work. EPSON S1C63454 TECHNICAL MANUAL...
Page 109: Chapter Electrical Characteristics
( Ta=-20 to 70°C ) Item Symbol Condition Min. Typ. Max. Unit Supply voltage OSC3 oscillation OFF OSC1 CR oscillation OSC3 oscillation ON Oscillation frequency Crystal oscillation – 32.768 – OSC1 CR oscillation CR oscillation 1,800 OSC3 Ceramic oscillation 4,100 EPSON S1C63454 TECHNICAL MANUAL...
Page 110: Dc Characteristics
High level output current (2) =0.9·V Low level output current (1) =0.1·V R00–03, P00–03, P10–13 Low level output current (2) =0.1·V µA Common output current -0.05V COM0–16 µA +0.05V µA Segment output current -0.05V SEG0–39 µA +0.05V EPSON S1C63454 TECHNICAL MANUAL...
Page 111: Analog Circuit Characteristics And Power Current Consumption
LC0–3="13" 2.34 LC0–3="14" 2.37 LC0–3="15" 2.40 Connect 1 MΩ load resistor between V and V 3/2·V 3/2·V ×0.95 (without panel load) Connect 1 MΩ load resistor between V and V 2·V 2·V ×0.95 (without panel load) EPSON S1C63454 TECHNICAL MANUAL...
Page 112 µA During execution (4 MHz ceramic oscillation), 1,000 1,200 LCD power ON (V standard) µA During execution (1,800 kHz CR oscillation), 1,000 LCD power ON (V standard) ∗1 VDC = "0" ∗2 OSCC = "0" EPSON S1C63454 TECHNICAL MANUAL...
Page 113: Oscillation Characteristics
Unless otherwise specified: =3.0V, V =0V, R =34kΩ, Ta=-20 to 70°C Item Symbol Condition Min. Typ. Max. Unit Oscillation frequency dispersion 1,800kHz OSC3 Oscillation start voltage Vsta Oscillation start time =2.2 to 6.4V Oscillation stop voltage Vstp EPSON S1C63454 TECHNICAL MANUAL...
Page 114 = 2.2 to 6.4 V 2.1M = 0 V Ta = 25°C 2.0M Typ. value 1.9M 1.8M 1.7M 1.6M 1.5M 1.4M 1.3M 1.2M 1.1M 1.0M 0.9M 100k 110k 120k Resistor value for CR oscillation R [Ω] EPSON S1C63454 TECHNICAL MANUAL...
Page 115: Serial Interface Ac Characteristics
Transmitting data output delay time Receiving data input set-up time Receiving data input hold time Note that the maximum clock frequency is limited to 1 MHz. <Master mode> SCLK OUT SOUT <Slave mode> SCLK IN SOUT EPSON S1C63454 TECHNICAL MANUAL...
Page 116: Timing Chart
Note: When the OSC1 oscillation circuit has been selected as the CR oscillation circuit, it is not neces- sary to set the VDC register. Whether the VDC register value is "1" or "0" does not matter. EPSON S1C63454 TECHNICAL MANUAL...
Page 117: Package
CHAPTER 8: PACKAGE CHAPTER ACKAGE 8.1 Plastic Package QFP15-100pin (Unit: mm) ±0.4 ±0.1 INDEX +0.1 0.18 –0.05 +0.05 0.125 –0.025 0° 10° ±0.2 The dimensions are subject to change without notice. EPSON S1C63454 TECHNICAL MANUAL...
Page 118: Ceramic Package For Test Samples
CHAPTER 8: PACKAGE 8.2 Ceramic Package for Test Samples QFP15-100pin (Unit: mm) ±0.30 17.00 12.00Typ. 0.50 0.20 GLASS ±0.30 CERAMIC 0.82 EPSON S1C63454 TECHNICAL MANUAL...
Page 119: Chapter Pad Layout
CHAPTER 9: PAD LAYOUT CHAPTER AYOUT 9.1 Diagram of Pad Layout (0, 0) Die No. 4.19 mm Chip thickness: 400 µm Pad opening: 85 µm EPSON S1C63454 TECHNICAL MANUAL...
Page 120: Pad Coordinates
1,971 SEG38 -1,971 -1,176 SEG14 -1,845 OSC2 1,971 SEG37 -1,971 -1,291 SEG13 1,072 -1,845 1,971 1,111 SEG36 -1,971 -1,406 SEG12 1,187 -1,845 OSC3 1,971 1,270 SEG11 1,302 -1,845 OSC4 1,971 1,385 SEG10 1,417 -1,845 1,971 1,514 EPSON S1C63454 TECHNICAL MANUAL...
Page 121: Appendix S5U1C63000P M Anual
These LEDs correspond one-to-one to the registers listed below. The LED lights when the data is logic "1" and goes out when the data is logic "0". VDC, OSCC, CLKCHG, SVDS0–3 ∗ , SVDON ∗ , LPWR, VCCHG ∗ SVDS0–3, SVDON: Used for the S1C63404/458/466/P466 EPSON S1C63454 TECHNICAL MANUAL...
Page 122 These pins allow you to monitor the clock waveform from the CR oscillation circuit with an oscillo- scope. Note that these pins always output a signal waveform whether or not the oscillation circuit is operating. RESET OSC3 monitor pin (red) OSC1 monitor pin (red) GND pin (black) EPSON S1C63454 TECHNICAL MANUAL...
Page 123 This control allows fine adjustment of the LCD drive voltage when the internal LCD power supply is selected by mask option. Note, however, that only the LCD contrast register can adjust the LCD drive voltage in the actual IC. EPSON S1C63454 TECHNICAL MANUAL...
Page 124: Connecting To The Target System
(80-pin/40-pin × 2, flat type). Take care when handling the connectors, since they conduct electrical power (V = +3.3 V). mark I/O connection cable CN1-1 (40-pin) CN1-2 (40-pin) To target board Fig. A.2.1 Connecting the S5U1C63000P to the target system EPSON S1C63454 TECHNICAL MANUAL...
Page 125 C2 *2 Cannot be connected C3 *2 Cannot be connected C4 *2 Cannot be connected C5 *2 Cannot be connected RESET ∗1: Can be used only for the S1C63404/458/466/P466 ∗2: Can be used only for the S1C63404/454/458/466/P466 EPSON S1C63454 TECHNICAL MANUAL...
Page 126: Usage Precautions
LCD power supply on/off circuit (LPWR) g) LCD constant-voltage change circuit (VCCHG) <Those that can only be counteracted by system or software> h) Current consumed by the internal pull-up resistors i) Input ports in a floating state EPSON S1C63454 TECHNICAL MANUAL...
Page 127 - Since the usable operating frequency range depends on the device's internal operating voltage, consult the technical manual for the S1C63404/454/455/458/466/P466 to ensure that the device will not be operated with an inappropriate combination of the operating frequency and the internal power supply. EPSON S1C63454 TECHNICAL MANUAL...
Page 128 - Do not change the value of the LPAGE bit (FF61H•D0) initialized to 0 as rewriting cause a malfunc- tion. ∗1: Applied when this board is used for the S1C63404/458/466/P466 ∗2: Applied when this board is used for the S1C63454/455 ∗3: Applied when this board is used for the S1C63455 EPSON...
Page 129 Central Phone: +852-2585-4600 Fax: +852-2827-4346 101 Virginia Street, Suite 290 Telex: 65542 EPSCO HX Crystal Lake, IL 60014, U.S.A. EPSON TAIWAN TECHNOLOGY & TRADING LTD. Phone: +1-815-455-7630 Fax: +1-815-455-7633 10F, No. 287, Nanking East Road, Sec. 3 Northeast Taipei 301 Edgewater Place, Suite 120...
Page 130 In pursuit of “Saving” Technology, Epson electronic devices. Our lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers’ dreams. Epson IS energy savings.
Page 131 S1C63454 Technical Manual ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epsondevice.com First issue March, 1998 Printed October, 2001 in Japan...

Epson S1C63454 Technical Manual

Chapter 3 Cpu, Rom, Ram

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