Epson S1C17704 Technical Manual page 385

Periperal Address
P port & 0x5217
port MUX
(8-bit device)
0x5218–0x521f –
0x5220
0x5221
0x5222
0x5223
0x5224
0x5225–0x522f –
0x5230
0x5231
0x5232
0x5233
0x5234
0x5235–0x527f –
0x52a0
0x52a1
0x52a2
0x52a3
0x52a4–0x52bf –
PWM & 0x5300
capture timer
0x5302
(16-bit device)
0x5304
0x5306
0x5308
0x530a
0x530c
0x530e–0x531f –
MISC register 0x5320
(8-bit device)
0x5321
0x5322
0x5323–0x533f –
Remote 0x5340
controller
0x5341
(8-bit device)
0x5342
0x5343
0x5344
0x5345
0x5346
0x5347
0x5348–0x535f –
S1C17 Core 0xffff80
0xffff84
I/O
0xffff90
Note: Do not access the "Reserved" address in the table above and unused areas in the peripheral area
that are not described in the table from the application program.
S1C17704 TECHNICAL MANUAL
Register name
P1_IFLG P1 Port Interrupt Flag Register
–
P2_IN P2 Port Input Data Register
P2_OUT P2 Port Output Data Register
P2_IO P2 Port I/O Direction Control Register
P2_PU P2 Port Pull-up Control Register
P2_SM P2 Port Schmitt Trigger Control Register
–
P3_IN P3 Port Input Data Register
P3_OUT P3 Port Output Data Register
P3_IO P3 Port I/O Direction Control Register
P3_PU P3 Port Pull-up Control Register
P3_SM P3 Port Schmitt Trigger Control Register
–
P0_PMUX P0 Port Function Select Register
P1_PMUX P1 Port Function Select Register
P2_PMUX P2 Port Function Select Register
P3_PMUX P3 Port Function Select Register
–
T16E_CA PWM Timer Compare Data A Register
T16E_CB PWM Timer Compare Data B Register
T16E_TC PWM Timer Counter Data Register
T16E_CTL PWM Timer Control Register
T16E_CLK PWM Timer Input Clock Select Register
T16E_IMSK PWM Timer Interrupt Mask Register
T16E_IFLG PWM Timer Interrupt Flag Register
–
MISC_FL FLASHC Control Register
MISC_SR SRAMC Control Register
MISC_OSC1 OSC1 Peripheral Control Register
–
REMC_CFG REMC Configuration Register
REMC_PSC REMC Prescaler Clock Select Register
REMC_CARH REMC H Carrier Length Setup Register
REMC_CARL REMC L Carrier Length Setup Register
REMC_ST REMC Status Register
REMC_LCNT REMC Length Counter Register
REMC_IMSK REMC Interrupt Mask Register
REMC_IFLG REMC Interrupt Flag Register
–
TTBR Vector Table Base Register
IDIR Processor ID Register
DBRAM Debug RAM Base Register
APPENDIX A LIST OF I/O REGISTERS
Indicates/resets the P1 port interrupt occur-
rence status.
Reserved
P2 port input data
P2 port output data
Selects the P2 port I/O direction.
Controls the P2 port pull-up resistor.
Controls the P2 port Schmitt trigger input.
Reserved
P3 port input data
P3 port output data
Selects the P3 port I/O direction.
Controls the P3 port pull-up resistor.
Controls the P3 port Schmitt trigger input.
Reserved
Selects the P0 port function.
Selects the P1 port function.
Selects the P2 port function.
Selects the P3 port function.
Reserved
Sets compare data A.
Sets compare data B.
Counter data
Sets the timer mode and starts/stops the timer.
Selects a prescaler output clock.
Enables/disables interrupt.
Indicates/resets interrupt occurrence status.
Reserved
Sets FLASHC access condition.
Sets the SRAMC access condition.
Selects the OSC1 peripheral operation in
debug mode.
Reserved
Selects/enables transmission/reception
Selects a prescaler output clock.
Sets up the H period of the carrier.
Sets up the L period of the carrier.
Transmit/receive bit
Sets the transmit/receive data length.
Enables/disables interrupt.
Indicates/resets interrupt occurrence status.
Reserved
Indicates the vector table base address.
Indicates the processor ID.
Indicates the debug RAM base address.
EPSON
Function
AP-3