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13.5 PWM & Capture Timer Run/Stop Control
Before starting the PWM & capture timer, set up the conditions as shown below.
(1) Select an operating mode (input clock). See Section 13.2.
(2) Set clock output conditions. See Section 13.6.
(3) Set up the interrupt level and enable the PWM & capture timer interrupt if the interrupt is used. See Section
13.7.
(4) Set a value to the counter or reset the counter to 0. See Section 13.3.
(5) Set compare data. See Section 13.4.
The PWM & capture timer provides T16ERUN (D0/T16E_CTL register) to run and stop the counter.
∗ T16ERUN: Timer Run/Stop Control Bit in the PWM Timer Control (T16E_CTL) Register (D0/0x5306)
The timer starts counting when 1 is written to T16ERUN. The clock input is disabled and the timer stops counting
when 0 is written to T16ERUN.
This control does not affect the counter data. Even when the timer has stopped counting, the counter retains its
count so that the timer can start counting again from that point.
When both T16ERUN and T16ERST are set to 1 at the same time, the timer starts counting after resetting the coun-
ter.
If the count of the counter matches the set value of the compare data A register during count-up, the timer outputs
the compare A match signal as a cause of interrupt.
When the counter matches compare data B, the timer outputs the compare B match signal as a cause of interrupt
and resets the counter. At the same time, the values set in the compare data buffer are loaded to the compare data
register if CBUFEN is set to 1. If the interrupt has been enabled, an interrupt request is sent to the interrupt control-
ler (ITC).
The counter continues counting up regardless of which interrupt has occurred. In the case of a compare B match,
the counter starts counting beginning with 0.
T16ERUN
T16ERST
T16E_CA
T16E_CB
Input clock
T16E_TC
Reset
S1C17704 TECHNICAL MANUAL
0
1
2
3
4
Compare A
interrupt
Figure 13.5.1 Basic Operation Timing of Counter
13 PWM & CAPTURE TIMER (T16E)
0x2
0x5
5
0
1
2
Reset and
Compare A
compare B
interrupt
interrupt
EPSON
3
4
5
0
1
Reset and
compare B
interrupt
13-5
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