I 2 C Interrupt - Epson S1C17704 Technical Manual

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20.6 I C Interrupt
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The I C module can generate the following two types of interrupts:
• Transmit buffer empty interrupt
• Receive buffer full interrupt
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The I C module has one interrupt signal to be output to the interrupt controller (ITC) and it is shared with the two
causes of interrupt.
Transmit buffer empty interrupt
Set the TINTE bit (D0/I2C_ICTL register) to 1 when using this interrupt. If TINTE is set to 0 (default), an
interrupt request by this cause will not be sent to the ITC.
∗ TINTE: Transmit Interrupt Enable Bit in the I
When the transmit data set in RTDT[7:0] (D[7:0]/I2C_DAT register) is transferred to the shift register, the I
module outputs an interrupt request pulse to the ITC if the transmit buffer empty interrupt has been enabled
(TINTE = 1).
∗ RTDT[7:0]: Receive/Transmit Data Bits in the I
If other interrupt conditions are satisfied, an interrupt is generated.
Receive buffer full interrupt
Set the RINTE bit (D1/I2C_ICTL register) to 1 when using this interrupt. If RINTE is set to 0 (default), an
interrupt request by this cause will not be sent to the ITC.
∗ RINTE: Receive Interrupt Enable Bit in the I
When data received in the shift register is loaded to RTDT[7:0], the I
pulse to the ITC if the receive buffer full interrupt has been enabled (RINTE = 1).
If other interrupt conditions are satisfied, an interrupt is generated.
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ITC registers for I C interrupts
The following shows the control bits of the ITC provided for the I
Interrupt flag
∗ IIFT7: I
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C Interrupt Flag in the Interrupt Flag (ITC_IFLG) Register (D15/0x4300)
Interrupt enable bit
∗ IIEN7: I
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C Interrupt Enable Bit in the Interrupt Enable (ITC_EN) Register (D15/0x4302)
Interrupt level setup bits
∗ IILV7[2:0]: I
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C Interrupt Level Bits in the Internal Interrupt Level Setup (ITC_ILV3) Register 3 (D[10:8]/0x4314)
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When the I C outputs an interrupt request pulse, the interrupt flag IIFT7 is set to 1.
If the interrupt enable bit IIEN7 has been set to 1, the ITC sends an interrupt request to the S1C17 Core. To
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disable the I C interrupt, set the IIEN7 bit to 0.
The IIFT7 flag is always set to 1 by the I
when set to 0).
The interrupt level setup bits IILV7[2:0] set the interrupt level (0 to 7) of the I
S1C17704 TECHNICAL MANUAL
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C Interrupt Control (I2C_ICTL) Register (D0/0x4346)
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C Data (I2C_DAT) Register (D[7:0]/0x4344)
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C Interrupt Control (I2C_ICTL) Register (D1/0x4346)
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C interrupt request pulse, regardless of how the IIEN7 bit is set (even
EPSON
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C module outputs an interrupt request
C module:
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C interrupt.
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20 I C
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C
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