Epson S1C17704 Technical Manual page 252

18 UART
Receive error interrupt
Set the REIEN bit (D6/UART_CTL register) to 1 when using this interrupt. If REIEN is set to 0 (default), an
interrupt request by this cause will not be sent to the ITC.
∗ REIEN: Receive Error Interrupt Enable Bit in the UART Control (UART_CTL) Register (D6/0x4104)
When a parity, framing, or overrun error is detected during data reception, the UART sets the error flag listed
below to 1 and outputs an interrupt request pulse to the ITC if the receive error interrupt has been enabled (REIEN
= 1).
∗ PER: Parity Error Flag in the UART Status (UART_ST) Register (D5/0x4100)
∗ FER: Framing Error Flag in the UART Status (UART_ST) Register (D6/0x4100)
∗ OER: Overrun Error Flag in the UART Status (UART_ST) Register (D4/0x4100)
If other interrupt conditions are satisfied, an interrupt is generated.
The UART interrupt handler routine should read the error flags to check if the interrupt has occurred due to a
receive error or another cause. When an error flag has been set to 1, the UART interrupt handler routine should
execute an error recovery process.
ITC registers for UART interrupts
The following shows the control bits of the ITC provided for the UART:
Interrupt flag
∗ IIFT4: UART Interrupt Flag in the Interrupt Flag (ITC_IFLG) Register (D12/0x4300)
Interrupt enable bits
∗ IIEN4: UART Interrupt Enable Bit in the Interrupt Enable (ITC_EN) Register (D12/0x4302)
Interrupt level setup bits
∗ IILV4[2:0]: UART Interrupt Level Bits in the Internal Interrupt Level Setup (ITC_ILV2) Register 2
(D[2:0]/0x4312)
When the UART outputs an interrupt request pulse, the corresponding interrupt flag is set to 1.
If the interrupt enable bit corresponding to that interrupt flag has been set to 1, the ITC sends an interrupt
request to the S1C17 Core. To disable the UART interrupt, set the interrupt enable bit to 0. The interrupt flag is
always set to 1 by the UART interrupt request pulse, regardless of how the interrupt enable register is set (even
when set to 0).
The interrupt level setup bits set the interrupt level (0 to 7) of the UART interrupt.
An interrupt request to the S1C17 Core is accepted only when all the conditions described below are met.
• The interrupt enable bit is set to 1.
• The IE (Interrupt Enable) bit of the PSR (Processor Status Register) in the S1C17 Core is set to 1.
• The UART interrupt has a higher interrupt level than the value that is set in the IL field of the PSR.
• No other cause of interrupt having higher priority, such as NMI, has occurred.
For details on these interrupt control registers, as well as the device operation when an interrupt has occurred,
see Chapter 6, "Interrupt Controller (ITC)."
Interrupt vector
The following shows the vector number and vector address for the UART interrupt:
Vector number: 16 (0x10)
Vector address: 0x8040
18-10
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S1C17704 TECHNICAL MANUAL