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6.3 Control of Maskable Interrupts
6.3.1 Enabling ITC
Before the ITC can be used, set the ITEN bit (D0/ITC_CTL register) to 1.
∗ ITEN: ITC Enable Bit in the ITC Control (ITC_CTL) Register (D0/0x4304)
6.3.2 Interrupt Request from Peripheral Module and Interrupt Flag
When an enabled interrupt cause occurs in a peripheral module, the module sends an interrupt request signal to the
ITC. The interrupt request signal sets the interrupt flag in the ITC corresponding to the cause of interrupt to 1. The
interrupt flag holds 1 until it is reset to 0 to indicate that an interrupt request has sent from the peripheral module.
The flag status can be read from the ITC_IFLG register (0x4300).
Table 6.3.2.1 lists the relationship between the causes of interrupt and the interrupt flags.
Vector No.
4
P0 port interrupt: P00–P07 port inputs
5
P1 port interrupt: P10–P17 port inputs
6
Stopwatch timer interrupt: 100 Hz/10 Hz/1 Hz signal
7
Clock timer interrupt: 32 Hz/8 Hz/2 Hz/1 Hz signal
8
8-bit OSC1 timer interrupt: compare match
9
SVD interrupt: low supply voltage detection
10
LCD interrupt: frame signal
11
PWM & capture timer interrupt: compare A/compare B match
12
8-bit timer interrupt: timer underflow
13
16-bit timer Ch.0 interrupt: timer underflow
14
16-bit timer Ch.1 interrupt: timer underflow
15
16-bit timer Ch.2 interrupt: timer underflow
16
UART interrupt: transmit buffer empty/receive buffer full/receive error
17
Remote controller interrupt: data length counter underflow/input rising
edge/input falling edge
18
SPI interrupt: transmit buffer empty/receive buffer full
2
19
I
C interrupt: transmit buffer empty/receive buffer full
The ITC uses the interrupt flags to generate an interrupt to the S1C17 Core.
When an interrupt flag is set to 1, the ITC sends the interrupt request, interrupt level and vector number signals to
the S1C17 Core if the interrupt has been enabled (see the next section).
The interrupt flag that has been set to 1 can be reset by writing 1. Reset the interrupt flag to 0 in the interrupt
handler. If the interrupt handler does not reset the interrupt flag, the same interrupt will be generated again when
the interrupt handling has finished (interrupts are disabled during interrupt handling and enabled by executing the
reti instruction placed at the end of the interrupt handler).
Note, however, that the interrupt flags (EIFT0–EIFT7) for the level triggered interrupts (see Section 6.3.5) cannot
be reset by writing 1. Those interrupt flags are reset when the interrupt signal is negated by the interrupt source.
For the occurrence conditions of the causes of interrupt and the module specific settings, refer to the section that
describes the interrupt source module.
S1C17704 TECHNICAL MANUAL
Table 6.3.2.1 Causes of Hardware Interrupt and Interrupt Flags
Cause of hardware interrupt
6 INTERRUPT CONTROLLER (ITC)
EPSON
Interrupt flag
EIFT0 (D0/ITC_IFLG register)
EIFT1 (D1/ITC_IFLG register)
EIFT2 (D2/ITC_IFLG register)
EIFT3 (D3/ITC_IFLG register)
EIFT4 (D4/ITC_IFLG register)
EIFT5 (D5/ITC_IFLG register)
EIFT6 (D6/ITC_IFLG register)
EIFT7 (D7/ITC_IFLG register)
IIFT0 (D8/ITC_IFLG register)
IIFT1 (D9/ITC_IFLG register)
IIFT2 (D10/ITC_IFLG register)
IIFT3 (D11/ITC_IFLG register)
IIFT4 (D12/ITC_IFLG register)
IIFT5 (D13/ITC_IFLG register)
IIFT6 (D14/ITC_IFLG register)
IIFT7 (D15/ITC_IFLG register)
6-3
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